ARM Ltd. Musca_B1 2025.07.15 ARM 32-bit v8-M Mainline based device CM33 r0p2 little true 4 false 8 32 CODE_SRAM_MPC Code SRAM Memory Protection Controller SRAM_MPC 0x52100000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 32 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 32 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C 32 read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index register 0x10 32 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 1 bit[3_0] Block size 0 4 CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF CTRL MPC Control register 0x0 32 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 1 bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 INT_CLEAR Interrupt clear 0x24 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 32 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 32 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x60 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Peripheral ID 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF DUALTIMER Dual Timer Timer 0x40002000 0x0 0x3C registers n DUALTIMER Dual Timer 5 TIMER1BGLOAD Timer 1 Background Load Register 0x18 read-write n 0x0 0xFFFFFFFF TIMER1CONTROL Timer 1 Control Register 0x8 read-write n 0x20 0xFFFFFFFF InterruptEnable Interrupt Enable bit. 5 1 Disable Interrupt is disabled. 0 Enable Interrupt is enabled. 1 OneShotCount Selects one-shot or wrapping counter mode. 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerEnable Timer Enable Enable bit. 7 1 Disable Timer is disabled. 0 Enable Timer is enabled. 1 TimerMode Timer Mode bit. 6 1 Free-Running Free-Running timer mode. 0 Periodic Periodic timer mode. 1 TimerPre Timer prescale bits. 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 TimerSize Selects 16-bit or 32- bit counter operation. 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TIMER1INTCLR Timer 1 Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear TIMER1LOAD Timer 1 Load Register 0x0 read-write n 0x0 0xFFFFFFFF TIMER1MIS Timer 1 Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Timer Interrupt 0 1 TIMER1RIS Timer 1 Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw Timer Interrupt 0 1 TIMER1VALUE Timer 1 Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF TIMER2BGLOAD Timer 2 Background Load Register 0x38 read-write n 0x0 0xFFFFFFFF TIMER2CONTROL Timer 2 Control Register 0x28 read-write n 0x20 0xFFFFFFFF InterruptEnable Interrupt Enable bit. 5 1 Disable Interrupt is disabled. 0 Enable Interrupt is enabled. 1 OneShotCount Selects one-shot or wrapping counter mode. 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerEnable Timer Enable Enable bit. 7 1 Disable Timer is disabled. 0 Enable Timer is enabled. 1 TimerMode Timer Mode bit. 6 1 Free-Running Free-Running timer mode. 0 Periodic Periodic timer mode. 1 TimerPre Timer prescale bits. 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 TimerSize Selects 16-bit or 32- bit counter operation. 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TIMER2INTCLR Timer 2 Interrupt Clear Register 0x2C write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear TIMER2LOAD Timer 2 Load Register 0x20 read-write n 0x0 0xFFFFFFFF TIMER2MIS Timer 2 Mask Interrupt Status Register 0x34 read-only n 0x0 0xFFFFFFFF MIS Masked Timer Interrupt 0 1 TIMER2RIS Timer 2 Raw Interrupt Status Register 0x30 read-only n 0x0 0xFFFFFFFF RIS Raw Timer Interrupt 0 1 TIMER2VALUE Timer 2 Value Register 0x24 read-only n 0xFFFFFFFF 0xFFFFFFFF DUALTIMER_Secure Dual Timer (Secure) Timer 0x50002000 0x0 0x3C registers n TIMER1BGLOAD Timer 1 Background Load Register 0x18 read-write n 0x0 0xFFFFFFFF TIMER1CONTROL Timer 1 Control Register 0x8 read-write n 0x20 0xFFFFFFFF InterruptEnable Interrupt Enable bit. 5 1 Disable Interrupt is disabled. 0 Enable Interrupt is enabled. 1 OneShotCount Selects one-shot or wrapping counter mode. 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerEnable Timer Enable Enable bit. 7 1 Disable Timer is disabled. 0 Enable Timer is enabled. 1 TimerMode Timer Mode bit. 6 1 Free-Running Free-Running timer mode. 0 Periodic Periodic timer mode. 1 TimerPre Timer prescale bits. 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 TimerSize Selects 16-bit or 32- bit counter operation. 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TIMER1INTCLR Timer 1 Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear TIMER1LOAD Timer 1 Load Register 0x0 read-write n 0x0 0xFFFFFFFF TIMER1MIS Timer 1 Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Timer Interrupt 0 1 TIMER1RIS Timer 1 Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw Timer Interrupt 0 1 TIMER1VALUE Timer 1 Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF TIMER2BGLOAD Timer 2 Background Load Register 0x38 read-write n 0x0 0xFFFFFFFF TIMER2CONTROL Timer 2 Control Register 0x28 read-write n 0x20 0xFFFFFFFF InterruptEnable Interrupt Enable bit. 5 1 Disable Interrupt is disabled. 0 Enable Interrupt is enabled. 1 OneShotCount Selects one-shot or wrapping counter mode. 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerEnable Timer Enable Enable bit. 7 1 Disable Timer is disabled. 0 Enable Timer is enabled. 1 TimerMode Timer Mode bit. 6 1 Free-Running Free-Running timer mode. 0 Periodic Periodic timer mode. 1 TimerPre Timer prescale bits. 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 TimerSize Selects 16-bit or 32- bit counter operation. 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TIMER2INTCLR Timer 2 Interrupt Clear Register 0x2C write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear TIMER2LOAD Timer 2 Load Register 0x20 read-write n 0x0 0xFFFFFFFF TIMER2MIS Timer 2 Mask Interrupt Status Register 0x34 read-only n 0x0 0xFFFFFFFF MIS Masked Timer Interrupt 0 1 TIMER2RIS Timer 2 Raw Interrupt Status Register 0x30 read-only n 0x0 0xFFFFFFFF RIS Raw Timer Interrupt 0 1 TIMER2VALUE Timer 2 Value Register 0x24 read-only n 0xFFFFFFFF 0xFFFFFFFF EFLASH0_MPC EFlash0 Memory Protection Controller SRAM_MPC 0x52200000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 32 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 32 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C 32 read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index register 0x10 32 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 1 bit[3_0] Block size 0 4 CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF CTRL MPC Control register 0x0 32 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 1 bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 INT_CLEAR Interrupt clear 0x24 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 32 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 32 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x60 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Peripheral ID 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF EFLASH1_MPC EFlash1 Memory Protection Controller SRAM_MPC 0x52300000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 32 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 32 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C 32 read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index register 0x10 32 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 1 bit[3_0] Block size 0 4 CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF CTRL MPC Control register 0x0 32 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 1 bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 INT_CLEAR Interrupt clear 0x24 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 32 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 32 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x60 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Peripheral ID 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF GPIO0 General-purpose I/O 0 GPIO 0x41000000 0x0 0x3C registers n GPIO0 GPIO 0 combined 68 ALTFUNCCLR Alternate function clear Register 0x1C read-write n 0x0 0xFFFFFFFF ALTFUNCSET Alternate function set Register 0x18 read-write n 0x0 0xFFFFFFFF DATA Data Register 0x0 read-write n 0x0 0xFFFFFFFF DATAOUT Data Output Register 0x4 read-write n 0x0 0xFFFFFFFF INTCLEAR Interrupt CLEAR Register INTSTATUS 0x38 write-only n 0x0 0xFFFFFFFF oneToClear INTENCLR Interrupt enable clear Register 0x24 read-write n 0x0 0xFFFFFFFF INTENSET Interrupt enable set Register 0x20 read-write n 0x0 0xFFFFFFFF INTPOLCLR Polarity-level, edge interrupt configuration clear Register 0x34 read-write n 0x0 0xFFFFFFFF INTPOLSET Polarity-level, edge interrupt configuration set Register 0x30 read-write n 0x0 0xFFFFFFFF INTSTATUS Interrupt Status Register 0x38 read-only n 0x0 0xFFFFFFFF INTTYPECLR Interrupt type clear Register 0x2C read-write n 0x0 0xFFFFFFFF INTTYPESET Interrupt type set Register 0x28 read-write n 0x0 0xFFFFFFFF OUTENCLR Ouptut enable clear Register 0x14 read-write n 0x0 0xFFFFFFFF OUTENSET Ouptut enable set Register 0x10 read-write n 0x0 0xFFFFFFFF GPIO0_Secure General-purpose I/O 0 (Secure) GPIO 0x51000000 0x0 0x3C registers n ALTFUNCCLR Alternate function clear Register 0x1C read-write n 0x0 0xFFFFFFFF ALTFUNCSET Alternate function set Register 0x18 read-write n 0x0 0xFFFFFFFF DATA Data Register 0x0 read-write n 0x0 0xFFFFFFFF DATAOUT Data Output Register 0x4 read-write n 0x0 0xFFFFFFFF INTCLEAR Interrupt CLEAR Register INTSTATUS 0x38 write-only n 0x0 0xFFFFFFFF oneToClear INTENCLR Interrupt enable clear Register 0x24 read-write n 0x0 0xFFFFFFFF INTENSET Interrupt enable set Register 0x20 read-write n 0x0 0xFFFFFFFF INTPOLCLR Polarity-level, edge interrupt configuration clear Register 0x34 read-write n 0x0 0xFFFFFFFF INTPOLSET Polarity-level, edge interrupt configuration set Register 0x30 read-write n 0x0 0xFFFFFFFF INTSTATUS Interrupt Status Register 0x38 read-only n 0x0 0xFFFFFFFF INTTYPECLR Interrupt type clear Register 0x2C read-write n 0x0 0xFFFFFFFF INTTYPESET Interrupt type set Register 0x28 read-write n 0x0 0xFFFFFFFF OUTENCLR Ouptut enable clear Register 0x14 read-write n 0x0 0xFFFFFFFF OUTENSET Ouptut enable set Register 0x10 read-write n 0x0 0xFFFFFFFF GPTIMER General-Purpose Timer Timer 0x4010C000 0x0 0x20 registers n GPTIMERINT1 General-Purpose Timer (Comparator 1) 72 GPTALARM0 ALARM0 data value register 0x10 read-write n 0x0 0xFFFFFFFF GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM1 ALARM1 data value register 0x14 read-write n 0x0 0xFFFFFFFF GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTCOUNTER Counter data value register 0x1C read-only n 0x0 0xFFFFFFFF GPTCOUNTER Current value of 32-bit Timer Counter 0 32 GPTINTC Interrupt clear register 0x8 read-write n 0x0 0xFFFFFFFF GPTINTC Writing 0b1 disables the ALARM[n] interrupt 0 2 GPTINTM Masked interrupt status register 0x4 read-write n 0x0 0xFFFFFFFF GPTINTM Current masked status of the interrupt 0 2 GPTINTR Raw interrupt status register 0x18 read-only n 0x0 0xFFFFFFFF GPTINTR Raw interrupt state, before masking of GPTINTR interrupt 0 3 GPTRESET Control Reset Register 0x0 read-only n 0x0 0xFFFFFFFF GPTRESET CPU0 interrupt status 0 2 GPTIMER_Secure General-Purpose Timer (Secure) Timer 0x5010C000 0x0 0x20 registers n GPTALARM0 ALARM0 data value register 0x10 read-write n 0x0 0xFFFFFFFF GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value 0 32 GPTALARM1 ALARM1 data value register 0x14 read-write n 0x0 0xFFFFFFFF GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value 0 32 GPTCOUNTER Counter data value register 0x1C read-only n 0x0 0xFFFFFFFF GPTCOUNTER Current value of 32-bit Timer Counter 0 32 GPTINTC Interrupt clear register 0x8 read-write n 0x0 0xFFFFFFFF GPTINTC Writing 0b1 disables the ALARM[n] interrupt 0 2 GPTINTM Masked interrupt status register 0x4 read-write n 0x0 0xFFFFFFFF GPTINTM Current masked status of the interrupt 0 2 GPTINTR Raw interrupt status register 0x18 read-only n 0x0 0xFFFFFFFF GPTINTR Raw interrupt state, before masking of GPTINTR interrupt 0 3 GPTRESET Control Reset Register 0x0 read-only n 0x0 0xFFFFFFFF GPTRESET CPU0 interrupt status 0 2 iCache Cache Cache 0x50010000 0x0 0x1000 registers n CIDR0 Component ID Register 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID Register 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID Register 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID Register 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF ICCTRL Instruction Cache Control Register 0x4 read-write n 0x0 0xFFFFFFFF CACHEEN Enable Cache 0 1 read-write Disabled All accesses bypass the cache 0 Enabled Caching is enabled 1 FINV Full Cache Invalidate 2 1 write-only Invalidate Triggers the instruction cache to start invalidating all cache lines 1 HALLOC Enable Handler Allocation 5 1 read-write LOW All incoming handler code fetches are not allocated a cache line if a miss occurs 0 HIGH Handler code access is treated like any other code access arriving at its interface 1 STATC Clear Statistic values 4 1 write-only Clear Triggers the instruction cache to start clear all cache statistic counters 1 STATEN Enable Statistic function 3 1 read-write Disabled Cache statistic counters are disabled 0 Enabled Cache statistic counters are enabled 1 ICDBGFILLERR Address where the latest fill error was seen 0x10C read-only n 0x0 0xFFFFFFFF ICHWPARAMS Hardware Parameter Register 0x0 read-only n 0x0 0xFFFFFFFF COFFSET Cacheable Offset Address 16 16 read-only COFFSIZE Cacheable Block Size 12 4 read-only CSIZE Cache size: Defines the size of the instruction cache 0 4 read-only DMA Presence of DMA Engine 5 1 read-only Unsupport The Instruction cache does not support pre-fetch and locking 0 Support The Instruction cache supports pre-fetch and locking 1 INVMAT Indicates whether invalidate cache line on write match is enabled 6 1 read-only Enabled Indicates Invalidate Cache Line on Write Match is enabled 1 STATS Presence of Statistic Functionality 4 1 read-only ICIRQEN Interrupt Enable register 0x108 read-write n 0x0 0xFFFFFFFF CDC_EN Cache Disable Complete IRQ Enable 1 1 read-write Disabled Disable the Cache Disable Complete IRQ 0 Enabled Enable the Cache Disable Complete IRQ 1 CEC_EN Cache Enable Complete IRQ Enable 2 1 read-write Disabled Disable the Cache Enable Complete IRQ 0 Enabled Enable the Cache Enable Complete IRQ 1 CFE_EN Cache Fill Error IRQ Enable 3 1 read-write Disabled Disable the Cache Fill Error IRQ 0 Enabled Enable the Cache Fill Error IRQ 1 IC_EN Invalidate Complete IRQ Enable 0 1 read-write Disabled Disable the Invalidate Complete IRQ 0 Enabled Enable the Invalidate Complete IRQ 1 SS_EN Statistics Saturated Enable 5 1 read-write Disabled Disable the Statistics Saturated 0 Enabled Enable the Statistics Saturated 1 SV_EN Security violation IRQ Enable 4 1 read-write Disabled Disable the Security violation IRQ 0 Enabled Enable the Security violation IRQ 1 ICIRQSCLR Interrupt Status Clear register 0x104 write-only n 0x0 0xFFFFFFFF CDC_CLR Cache Disable Complete IRQ Status Clear 1 1 write-only Clear Clear Cache Disable Complete IRQ Status 1 CEC_CLR Cache Enable Complete IRQ Status Clear 2 1 write-only Clear Clear the Cache Enable Complete IRQ Status 1 CFE_CLR Cache Fill Error IRQ Status Clear 3 1 write-only Clear Clear the Cache Fill Error IRQ Status 1 IC_CLR Invalidate Complete IRQ Status Clear 0 1 write-only Clear Clear the Invalidate Complete IRQ Status 1 SS_CLR Statistics Saturated Status Clear 5 1 write-only Clear Clear the Statistics Saturated Status 1 SV_CLR Security violation IRQ Status Clear 4 1 write-only Clear Clear the Security violation IRQ Status 1 ICIRQSTAT Interrupt Request Status Register 0x100 read-only n 0x0 0xFFFFFFFF CDC_STATUS Cache Disable Complete IRQ Status 1 1 read-only Completed Indicates that a request to disable the cache has been completed 1 CEC_STATUS Cache Enable Complete IRQ Status 2 1 read-only Completed Indicates that a request to enable the cache has been completed 1 CFE_STATUS Cache Fill Error IRQ Status 3 1 read-only Err_Occurred Indicates that a bus error occurred while filling a cache line 1 IC_STATUS Invalidate Complete IRQ Status 0 1 read-only Completed Indicates that a cache invalidation process has been completed 1 SS_STATUS Statistics Saturated Status 5 1 read-only Saturated Indicates that the internal statistic counters have saturated 1 SV_STATUS Security violation IRQ Status 4 1 read-only ICSH Instruction Cache Statistic Hit Count register 0x300 read-only n 0x0 0xFFFFFFFF ICSM Instruction Cache Statistic Miss Count register 0x304 read-only n 0x0 0xFFFFFFFF ICSUC Instruction Cache Statistic Uncached Count register 0x308 read-only n 0x0 0xFFFFFFFF PIDR0 Product ID Register 0 0xFE0 32 read-only n 0x57 0xFFFFFFFF PIDR1 Product ID Register 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Product ID Register 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF PIDR3 Product ID Register 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF PIDR4 Product ID Register 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF PIDR5 Product ID Register 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF PIDR6 Product ID Register 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Product ID Register 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF NSPCTRL Non-secure Privilege Control Block NSPCTRL 0x40080000 0x0 0x1000 registers n AHBNSPPPC0 Non-Secure Unprivileged Access AHB slave Peripheral Protection Control #0 0x90 32 read-write n 0x0 0xFFFFFFFF AHBNSPPPCEXP0 Expansion 0 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA0 32 read-write n 0x0 0xFFFFFFFF AHBNSPPPCEXP1 Expansion 1 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA4 32 read-write n 0x0 0xFFFFFFFF AHBNSPPPCEXP2 Expansion 2 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA8 32 read-write n 0x0 0xFFFFFFFF AHBNSPPPCEXP3 Expansion 3 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xAC 32 read-write n 0x0 0xFFFFFFFF APBNSPPPC0 Non-Secure Unprivileged Access APB slave Peripheral Protection Control 0 0xB0 32 read-write n 0x0 0xFFFFFFFF APBNSPPPC1 Non-Secure Unprivileged Access APB slave Peripheral Protection Control 1 0xB4 32 read-write n 0x0 0xFFFFFFFF APBNSPPPCEXP0 Expansion 0 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xC0 32 read-write n 0x0 0xFFFFFFFF APBNSPPPCEXP1 Expansion 1 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xC4 32 read-write n 0x0 0xFFFFFFFF APBNSPPPCEXP2 Expansion 2 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xC8 32 read-write n 0x0 0xFFFFFFFF APBNSPPPCEXP3 Expansion 3 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xCC 32 read-write n 0x0 0xFFFFFFFF CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x53 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x0 0xFFFFFFFF PWM PWM_IP6512 PWM 0x40107000 0x0 0x20 registers n PWMINT2 PWM2 interrupt 75 PWMCR PWM Control Register 0x0 read-write n 0x0 0xFFFFFFFF OUTPUT_SET Start stop bit for the pwm_output 0 1 read-write Disabled Set pwm_output continually high 0 Enabled Generate programmed waveform on pwm_output 1 PWMDI PWM Disable Interrupt Register 0x14 write-only n 0x0 0xFFFFFFFF Disable_BIT Determines whether the write accesses the Interrupt Disable register 0 1 write-only Disabled Disable the Interrupt generation 1 PWMEI PWM Enable Interrupt Register 0x10 write-only n 0x0 0xFFFFFFFF Enable_BIT Determines whether the write accesses the Interrupt Enable register 0 1 write-only Enabled Enable the Interrupt generation 1 PWMHR PWM High Iime Register. This register contains the number of system clock cycles for during which the pwm_output should be kept high in a PWM cycle 0x8 read-write n 0x0 0xFFFFFFFF PWMIS PWM Read Interrupt Status Register 0x1C read-only n 0x0 0xFFFFFFFF Status Reading from this address returns the current state of the PWM Interrupt output, and then sets the bit low 0 1 read-only Not active Interrupt is not active 0 Active Interrupt is active 1 PWMPR PWM Period Register. Number of system clock cycles indicating the period of PWM cycle.The minimum and maximum values have special significance. 0x0: pwm_output continually high 0xFFFFFFFF: pwm_output continually low 0x4 read-write n 0x0 0xFFFFFFFF PWMRI PWM Read Intr Enable Register.Reading from this address accesses the current state of the interrupt control registers 0x18 read-only n 0x0 0xFFFFFFFF Enable_BIT Check whether the Interrupt is Enabled 0 1 read-only Enabled Interrupt is Enabled 1 QSPIFCTRL QSPI Flash Controller QSPI 0x42800000 0x0 0xB0 registers n QSPIINTR QSPI interrupt 38 DEVREADINSTR Device Read Instruction Register 0x4 read-write n 0x3 0xFFFFFFFF ADDRTRTYPESSPI Address Transfer Type for Standard SPI modes 12 14 DATATRTYPESSPI Data Transfer Type for Standard SPI modes 16 18 DDRBITEN DDR Bit Enable 10 11 INSTRTYPE Instruction Type 8 10 MODEBITEN Mode Bit Enable 20 21 READDUMCLKCYCNUM Number of Dummy Clock Cycles required by device for Read Instruction 24 29 ROPCODE Read Opcode to use when not in XIP mode 0 8 DEVSIZE Device Size Configuration Register 0x14 read-write n 0x101002 0xFFFFFFFF ADDRBYTENUM Number of address bytes 0 4 BYTEPERBLKNUM Number of bytes per block 16 21 BYTEPERDEVPGNUM Number of bytes per device page 4 16 FDEVSIZECS0 Size of Flash Device connected to CS[0] pin 21 23 FDEVSIZECS1 Size of Flash Device connected to CS[1] pin 23 25 FDEVSIZECS2 Size of Flash Device connected to CS[2] pin 25 27 FDEVSIZECS3 Size of Flash Device connected to CS[3] pin 27 29 DEVWRITEINSTR Device Write Instruction Configuration Register 0x8 read-write n 0x2 0xFFFFFFFF ADDRTRTYPESSPI Address Transfer Type for Standard SPI modes 12 14 DATATRTYPESSPI Data Transfer Type for Standard SPI modes 16 18 WELDISABLE WEL Disable 8 9 WRITEDUMCLKCYCNUM Number of Dummy Clock Cycles required by device for Write Instruction 24 29 WROPCODE Write Opcode 0 8 FLASHCMDADDR Flash Command Address Register 0x94 read-write n 0x0 0xFFFFFFFF FLASHCMDCTRL Flash Command Control Register 0x90 read-write n 0x0 0xFFFFFFFF ADDRBYTENUM Number of Address Bytes 16 18 CMDADDREN Command Address Enable 19 20 CMDEXEC Execute the command 0 1 CMDEXINPROG Command execution in progress 1 2 CMDOPCODE Command Opcode 24 32 DUMCYCNUM Number of Dummy Cycles 7 12 MODEBITEN Mode Bit Enable 18 19 RDATABYTENUM Number of Read Data Bytes 20 23 RDATAEN Read Data Enable 23 24 WRDATABYTENUM Number of Write Data Bytes 12 15 WRDATAEN Write Data Enable 15 16 FLASHCMDRDATALOW Flash Command Read Data Register (Lower) 0xA0 read-only n 0x0 0xFFFFFFFF FLASHCMDRDATAUP Flash Command Read Data Register (Upper) 0xA4 read-only n 0x0 0xFFFFFFFF FLASHCMDWRDATALOW Flash Command Write Data Register (Lower) 0xA8 read-write n 0x0 0xFFFFFFFF FLASHCMDWRDATAUP Flash Command Write Data Register (Upper) 0xAC read-write n 0x0 0xFFFFFFFF QSPICFG QSPI Configuration Register 0x0 read-write n 0x80780081 0xFFFFFFFF AHBDECEN Enable AHB Decoder 23 24 CLKPHASE Clock phase, this maps to the standard SPI CPHA transfer format 2 3 CLKPOLARITY Clock polarity outside SPI word. This maps to the standard SPI CPOL transfer format 1 2 DTREN Enable DTR Protocol 24 25 ENAHBADDRRM Enable AHB Address Re-mapping 16 17 ENDIRACCCTR Enable Direct Access Controller 7 8 ENDMAPIF Enable DMA Peripheral Interface 15 16 ENTRXIPMODEIMM Enter XIP Mode immediately 18 19 ENTRXIPMODEONR Enter XIP Mode on next READ 17 18 LEGIPMODEEN Legacy IP Mode Enable 8 9 MAMOBRDIV Master mode baud rate divisor (2 to 32) 19 23 PERCSLINES Peripheral chip select lines 10 14 ss3 n_ss_out: 0b0111 0b0111 ssinactive n_ss_out: 0b1111 (no peripheral selected) 0b1111 ss2 n_ss_out: 0b1011 0bx011 ss1 n_ss_out: 0b1101 0bxx01 ss0 n_ss_out: 0b1110 0bxxx0 PERSELDEC Peripheral select decode 9 10 Disabled Only 1 of 4 selects n_ss_out is active 0 Enabled Allow external 4-to-16 decode 1 PHYMODEEN PHY Mode enable 3 4 PIPLIDLE Serial Interface and QSPI pipeline is IDLE 31 32 PIPLPHYEN Pipeline PHY Mode enable 25 26 QSPIEN QSPI Enable 0 1 WPPINDRV Set to drive the WP pin of Flash device 14 15 REMAPADDR Remap Address Register 0x24 read-write n 0x0 0xFFFFFFFF QSPIFCTRL_Secure QSPI Flash Controller (Secure) QSPI 0x52800000 0x0 0xB0 registers n DEVREADINSTR Device Read Instruction Register 0x4 read-write n 0x3 0xFFFFFFFF ADDRTRTYPESSPI Address Transfer Type for Standard SPI modes 12 14 DATATRTYPESSPI Data Transfer Type for Standard SPI modes 16 18 DDRBITEN DDR Bit Enable 10 11 INSTRTYPE Instruction Type 8 10 MODEBITEN Mode Bit Enable 20 21 READDUMCLKCYCNUM Number of Dummy Clock Cycles required by device for Read Instruction 24 29 ROPCODE Read Opcode to use when not in XIP mode 0 8 DEVSIZE Device Size Configuration Register 0x14 read-write n 0x101002 0xFFFFFFFF ADDRBYTENUM Number of address bytes 0 4 BYTEPERBLKNUM Number of bytes per block 16 21 BYTEPERDEVPGNUM Number of bytes per device page 4 16 FDEVSIZECS0 Size of Flash Device connected to CS[0] pin 21 23 FDEVSIZECS1 Size of Flash Device connected to CS[1] pin 23 25 FDEVSIZECS2 Size of Flash Device connected to CS[2] pin 25 27 FDEVSIZECS3 Size of Flash Device connected to CS[3] pin 27 29 DEVWRITEINSTR Device Write Instruction Configuration Register 0x8 read-write n 0x2 0xFFFFFFFF ADDRTRTYPESSPI Address Transfer Type for Standard SPI modes 12 14 DATATRTYPESSPI Data Transfer Type for Standard SPI modes 16 18 WELDISABLE WEL Disable 8 9 WRITEDUMCLKCYCNUM Number of Dummy Clock Cycles required by device for Write Instruction 24 29 WROPCODE Write Opcode 0 8 FLASHCMDADDR Flash Command Address Register 0x94 read-write n 0x0 0xFFFFFFFF FLASHCMDCTRL Flash Command Control Register 0x90 read-write n 0x0 0xFFFFFFFF ADDRBYTENUM Number of Address Bytes 16 18 CMDADDREN Command Address Enable 19 20 CMDEXEC Execute the command 0 1 CMDEXINPROG Command execution in progress 1 2 CMDOPCODE Command Opcode 24 32 DUMCYCNUM Number of Dummy Cycles 7 12 MODEBITEN Mode Bit Enable 18 19 RDATABYTENUM Number of Read Data Bytes 20 23 RDATAEN Read Data Enable 23 24 WRDATABYTENUM Number of Write Data Bytes 12 15 WRDATAEN Write Data Enable 15 16 FLASHCMDRDATALOW Flash Command Read Data Register (Lower) 0xA0 read-only n 0x0 0xFFFFFFFF FLASHCMDRDATAUP Flash Command Read Data Register (Upper) 0xA4 read-only n 0x0 0xFFFFFFFF FLASHCMDWRDATALOW Flash Command Write Data Register (Lower) 0xA8 read-write n 0x0 0xFFFFFFFF FLASHCMDWRDATAUP Flash Command Write Data Register (Upper) 0xAC read-write n 0x0 0xFFFFFFFF QSPICFG QSPI Configuration Register 0x0 read-write n 0x80780081 0xFFFFFFFF AHBDECEN Enable AHB Decoder 23 24 CLKPHASE Clock phase, this maps to the standard SPI CPHA transfer format 2 3 CLKPOLARITY Clock polarity outside SPI word. This maps to the standard SPI CPOL transfer format 1 2 DTREN Enable DTR Protocol 24 25 ENAHBADDRRM Enable AHB Address Re-mapping 16 17 ENDIRACCCTR Enable Direct Access Controller 7 8 ENDMAPIF Enable DMA Peripheral Interface 15 16 ENTRXIPMODEIMM Enter XIP Mode immediately 18 19 ENTRXIPMODEONR Enter XIP Mode on next READ 17 18 LEGIPMODEEN Legacy IP Mode Enable 8 9 MAMOBRDIV Master mode baud rate divisor (2 to 32) 19 23 PERCSLINES Peripheral chip select lines 10 14 ss3 n_ss_out: 0b0111 0b0111 ssinactive n_ss_out: 0b1111 (no peripheral selected) 0b1111 ss2 n_ss_out: 0b1011 0bx011 ss1 n_ss_out: 0b1101 0bxx01 ss0 n_ss_out: 0b1110 0bxxx0 PERSELDEC Peripheral select decode 9 10 Disabled Only 1 of 4 selects n_ss_out is active 0 Enabled Allow external 4-to-16 decode 1 PHYMODEEN PHY Mode enable 3 4 PIPLIDLE Serial Interface and QSPI pipeline is IDLE 31 32 PIPLPHYEN Pipeline PHY Mode enable 25 26 QSPIEN QSPI Enable 0 1 WPPINDRV Set to drive the WP pin of Flash device 14 15 REMAPADDR Remap Address Register 0x24 read-write n 0x0 0xFFFFFFFF QSPI_MPC QSPI Flash Memory Protection Controller SRAM_MPC 0x52000000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 32 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 32 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C 32 read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index register 0x10 32 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 1 bit[3_0] Block size 0 4 CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF CTRL MPC Control register 0x0 32 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 1 bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 INT_CLEAR Interrupt clear 0x24 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 32 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 32 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x60 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Peripheral ID 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF S32KTIMER S32K Timer Timer 0x4002F000 0x0 0x10 registers n S32KTIMER Timer 1 2 CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ENABLE Enable 0 1 Disable Timer is disabled 0 Enable Timer is enabled 1 EXTCLK External Clock Enable 2 3 Disable External Clock is disabled 0 Enable External Clock is enabled 1 EXTIN External Input as Enable 1 2 Disable External Input as Enable is disabled 0 Enable External Input as Enable is enabled 1 INTEN Interrupt Enable 3 4 Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 INTCLEAR Timer Interrupt clear register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF oneToClear INTSTATUS Timer Interrupt status register 0xC read-only n 0x0 0xFFFFFFFF RELOAD Counter Reload Value 0x8 read-write n 0x0 0xFFFFFFFF VALUE Current Timer Counter Value 0x4 read-write n 0x0 0xFFFFFFFF S32KTIMER_Secure S32K Timer (Secure) FLASHCNT 0x5002F000 0x0 0x28 registers n FLCACP Flashcnt accept register 0x4 32 read-write n 0x0 0x0 FAC - 0 8 write-only FLCADR Flashcnt address register 0x8 32 read-write n 0x0 0x0 FA - 2 32 read-write FLCBADR Flashcnt boot program address register 0x24 32 read-write n 0x0 0x0 BPA - 2 18 read-only FLCERA Flashcnt erase register 0x10 32 read-write n 0x0 0x0 FLE - 0 2 read-write Chip erase None 1 Block erase None 2 Sector erase None 3 FLCRSIZ Flashcnt size register 0x20 32 read-write n 0x0 0x0 FSI - 0 32 read-only FLCSTA Flashcnt status register 0x0 32 read-write n 0x0 0x0 BUSY Busy bit 0 1 read-only busy None 1 FLCWDA Flashcnt write data register 0xC 32 read-write n 0x0 0x0 FD - 0 32 write-only S32KWATCHDOG S32K Watchdog (Secure) WATCHDOG 0x5002E000 0x0 0xC04 registers n WDOGCONTROL Watchdog Control Register 0x8 read-write n 0x0 0xFFFFFFFF INTEN Enable the interrupt event 0 1 Disable Disable Watchdog interrupt 0 Enable Enable Watchdog interrupt. 1 RESEN Enable watchdog reset output 1 1 Disable Disable Watchdog reset 0 Enable Enable Watchdog reset 1 WDOGINTCLR Watchdog Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear WDOGLOAD Watchdog Load Register 0x0 read-write n 0xFFFFFFFF 0xFFFFFFFF WDOGLOCK Watchdog Lock Register 0xC00 read-write n 0x0 0xFFFFFFFF Access Enable register writes 1 31 Status Register write enable status 0 1 Enabled Write access to all other registers is enabled. This is the default. 0 Disabled Write access to all other registers is disabled. 1 WDOGMIS Watchdog Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Watchdog Interrupt 0 1 WDOGRIS Watchdog Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw watchdog Interrupt 0 1 WDOGVALUE Watchdog Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF SAU Security Attribution Unit SAU 0xE000EDD0 0x0 0x20 registers n CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ALLNS Security attribution if SAU disabled 1 2 Secure Memory is marked as secure 0 Non_Secure Memory is marked as non-secure 1 ENABLE Enable 0 1 Disable SAU is disabled 0 Enable SAU is enabled 1 RBAR Region Base Address Register 0xC read-write n 0x0 0xFFFFFFFF BADDR Base Address 5 32 RLAR Region Limit Address Register 0x10 read-write n 0x0 0xFFFFFFFF ENABLE SAU Region enabled 0 1 LADDR Limit Address 5 32 NSC Non-Secure Callable 1 2 RNR Region Number Register 0x8 read-write n 0x0 0xFFFFFFFF REGION Currently selected SAU region 0 8 SAU_Region_0 Select SAU Region 0 0 SAU_Region_1 Select SAU Region 1 1 SAU_Region_2 Select SAU Region 2 2 SAU_Region_3 Select SAU Region 3 3 SFSR Secure Fault Status Register 0x14 read-write n 0x0 0xFFFFFFFF AUVIOL Attribution unit violation flag 3 4 INVEP Invalid entry pointd 0 1 INVER Invalid exception return flag 2 3 INVIS Invalid integrity signature flag 1 2 INVTRAN Invalid transition flag 4 5 LSERR Lazy state error flag 7 8 LSPERR Lazy state preservation error flag 5 6 SFARVALID Secure fault address valid 6 7 TYPE Type Register 0x4 read-only n 0x0 0xFFFFFFFF SREGION Number of implemented SAU regions 0 8 SCC Serial Communication Controller SCC 0x5010B000 0x0 0x1000 registers n AZ_CODE_REMAP_MASK 0x1EC 32 read-write n 0xFFFFFF 0xFFFFFFFF az_code_remap_mask Alcatraz code remap mask 0 32 AZ_CODE_REMAP_OFFSET 0x1F0 32 read-write n 0x0 0xFFFFFFFF az_code_remap_offset Alcatraz code remap offset 0 32 AZ_CPU_VTOR 0x64 32 read-write n 0xA03800 0xFFFFFFFF AZ_CODE_REMAP Remap vector for Alcatraz Code address space 8 16 AZ_ROM_REMAP Remap vector for Alcatraz ROM address space. 0 8 AZ_SYS_REMAP Remap vector for Alcatraz System address space 16 24 AZ_CTRL 0x200 32 read-write n 0x600 0xFFFFFFFF AZ_BOOT_REMAP Alcatraz remap at boot 0 1 CHSEC_ISO_ENB Alcatraz CryptoCell Secure Frame Isolation enable 4 5 CHSEC_MISC_7 Alcatraz CryptoCell secure Secure Frame control 5 6 CPUWAIT Alcatraz CPU wait at boot: 1 2 DBGRESETn Alcatraz reset DBGRESETn 7 8 HRESETn Alcatraz reset HRESETn 8 9 REMOVE_CHACHA_ENGINE Alcatraz CryptoCell remove CHACHA engine 2 3 REMOVE_GHASH_ENGINE Alcatraz CryptoCell remove Ghash engine 3 4 SCC_nPORESETAON_nPORESET_SEL Alcatraz reset control 9 10 SCC_PSI_FEATURE_EN Value of SCC_PSI_FEATURE_EN from SCC 10 11 SCC_PSI_FEATURE_EN_SEL Select PSI_FEATURE_EN source 11 12 AZ_OTP_RD_DATA 0x210 32 read-write n 0x0 0xFFFFFFFF az_otp_rd_data Alcatraz OTP read data 0 32 AZ_ROM_REMAP_MASK 0x1E4 32 read-write n 0x1FFFF 0xFFFFFFFF az_rom_remap_mask Alcatraz ROM remap mask 0 32 AZ_ROM_REMAP_OFFSET 0x1E8 32 read-write n 0x1A200000 0xFFFFFFFF az_rom_remap_offset Alcatraz ROM remap offset 0 32 AZ_SYS_REMAP_MASK 0x1F4 32 read-write n 0x3FFFF 0xFFFFFFFF az_sys_remap_mask Alcatraz system remap mask 0 32 AZ_SYS_REMAP_OFFSET 0x1F8 32 read-write n 0x40010000 0xFFFFFFFF az_sys_remap_offset Alcatraz system remap offset 0 32 CHIP_ID 0x400 32 read-only n 0x7D00477 0xFFFFFFFF chip_id Component ID information 0 32 CLK_CTRL_ENABLE 0x30 32 read-write n 0xFFFF 0xFFFFFFFF ctrl_enable_1hz 0: Disable 1: Enable 0 1 ctrl_enable_dapswclk 0: Disable 1: Enable 1 2 ctrl_enable_gpiohclk 0: Disable 1: Enable 2 3 ctrl_enable_i2sclk0 0: Disable 1: Enable 3 4 ctrl_enable_i2sclk1 0: Disable 1: Enable 4 5 ctrl_enable_i2sclk2 0: Disable 1: Enable 5 6 ctrl_enable_mainclk 0: Disable 1: Enable 8 9 ctrl_enable_qspi_phy_clk 0: Disable 1: Enable 9 10 ctrl_enable_refclk 0: Disable 1: Enable 10 11 ctrl_enable_rm38kclk 0: Disable 1: Enable 11 12 ctrl_enable_sccclk 0: Disable 1: Enable 12 13 ctrl_enable_sdphyclk 0: Disable 1: Enable 13 14 ctrl_enable_testclk 0: Disable 1: Enable 15 16 CLK_CTRL_SEL 0x0 32 read-write n 0x72 0xFFFFFFFF ctrl_sel_test_mux_clk ctrl_sel_test_mux_clk 7 12 sel_dapswmux_clk 0: PRE_MUX_CLK 1: TCK 1 2 sel_mainmux_clk 0: PLL0_CLK 1: PRE_MUX_CLK 2 3 sel_premux_clk 0: 32k 1: FASTCLK 0 1 sel_refmux_clk 0: PRE_MUX_CLK 1: PRE_PLL_CLK 3 4 sel_rm38kmux_clk 0: REF_MUX_CLK 1: RM38K 4 5 sel_rm38p4_premux_clk 0: SYSSYSSUGCLK 1: NRM138P4 6 7 sel_sccmux_clk 0: SCCCLK 1: PRE_MUX_CLK 5 6 CLK_PLL_PREDIV_CTRL 0x4 32 read-write n 0x0 0xFFFFFFFF prediv_ctrl prediv_ctrl 0 10 CLK_POSTDIV_CTRL_FLASH 0xC 32 read-write n 0x1 0xFFFFFFFF postdiv_ctrl_flash_div postdiv_ctrl_flash_div 0 8 CLK_POSTDIV_CTRL_QSPI 0x10 32 read-write n 0x1 0xFFFFFFFF postdiv_ctrl_qspi_div postdiv_ctrl_qspi_div 0 8 CLK_POSTDIV_CTRL_RTC 0x14 32 read-write n 0xFFFFFFFF 0xFFFFFFFF postdiv_ctrl_rtc_div postdiv_ctrl_rtc_div 0 32 CLK_POSTDIV_CTRL_SD 0x18 32 read-write n 0x1 0xFFFFFFFF postdiv_ctrl_sd_div postdiv_ctrl_sd_div 0 8 CLK_POSTDIV_CTRL_TEST 0x1C 32 read-write n 0xA 0xFFFFFFFF postdiv_ctrl_test_div postdiv_ctrl_test_div 0 8 CLK_STATUS 0x34 32 read-only n 0x3 0xFFFFFFFF status_lock_signal_pll0_clk PLL Lock Status 1 2 status_out_clk_mainclk_ready Clock ready (active) 0 1 CLK_TEST_CTRL 0x54 32 read-write n 0x0 0xFFFFFFFF CLK_MAIN_FORCE_RDY CLK_MAIN_FORCE_RDY 6 7 CLK_TEST_EN 0: Not enable 1: Enable 5 6 CLK_TEST_SEL Select TESTMUX input 0 5 CPU0_VTOR 0x58 32 read-write n 0x10000000 0xFFFFFFFF CPU0_VTOR_SECURE Reset vector for CPU0 secure mode 7 32 CPU1_VTOR 0x60 32 read-write n 0x1A400000 0xFFFFFFFF CPU1_VTOR_SECURE Reset vector for CPU1 secure mode 7 32 CTRL_BYPASS_DIV 0x20 32 read-write n 0x1 0xFFFFFFFF bypass_div_pll_div_prediv_clk 0: Not bypass 1: bypass 0 1 bypass_qspi_div_clk 0: Not bypass 1: bypass 3 4 bypass_rtc_div_clk 0: Not bypass 1: bypass 4 5 bypass_sd_div_clk 0: Not bypass 1: bypass 5 6 bypass_test_div_clk 0: Not bypass 1: bypass 6 7 DBG_CTRL 0x48 32 read-write n 0x1F 0xFFFFFFFF DBG_DCU_FORCE SSE-200 debug ports control 30 32 SSE_200_DBGENIN 0: Not enable 1: Enable 0 1 SSE_200_NIDENIN 0: Not enable 1: Enable 1 2 SSE_200_SPIDENIN 0: Not enable 1: Enable 2 3 SSE_200_SPNIDENIN 0: Not enable 1: Enable 3 4 TODBGENSEL0 0: Enable 1: Mask or bypass 7 8 TODBGENSEL1 0: Enable 1: Mask or bypass 8 9 FLASH0_DOUT_0 0x1C0 32 read-only n 0xFFFFFFFF 0xFFFFFFFF scc_flash0_dout0 eFlash 0 data output[31:0] 0 32 FLASH0_DOUT_1 0x1C4 32 read-only n 0xFFFFFFFF 0xFFFFFFFF scc_flash0_dout1 eFlash 0 data output[63:32] 0 32 FLASH0_DOUT_2 0x1C8 32 read-only n 0xFFFFFFFF 0xFFFFFFFF scc_flash0_dout2 eFlash 0 data output[95:64] 0 32 FLASH0_DOUT_3 0x1CC 32 read-only n 0xFFFFFFFF 0xFFFFFFFF scc_flash0_dout3 eFlash 0 data output[127:96] 0 32 FLASH1_DOUT_0 0x1D0 32 read-only n 0xFFFFFFFF 0xFFFFFFFF scc_flash1_dout0 eFlash 1 data output[31:0] 0 32 FLASH1_DOUT_1 0x1D4 32 read-only n 0xFFFFFFFF 0xFFFFFFFF scc_flash1_dout1 eFlash 1 data output[63:32] 0 32 FLASH1_DOUT_2 0x1D8 32 read-only n 0xFFFFFFFF 0xFFFFFFFF scc_flash1_dout2 eFlash 1 data output[95:64] 0 32 FLASH1_DOUT_3 0x1DC 32 read-only n 0xFFFFFFFF 0xFFFFFFFF scc_flash1_dout3 eFlash 1 data output[127:96] 0 32 FLASH_DIN_0 0x1A0 32 read-write n 0x0 0xFFFFFFFF scc_flash_din0 eFlash 0 and eFlash 1 data input[31:0] 0 32 FLASH_DIN_1 0x1A4 32 read-write n 0x0 0xFFFFFFFF scc_flash_din1 eFlash 0 and eFlash 1 data input{63:32] 0 32 FLASH_DIN_2 0x1A8 32 read-write n 0x0 0xFFFFFFFF scc_flash_din2 eFlash 0 and eFlash 1 data input[95:64] 0 32 FLASH_DIN_3 0x1AC 32 read-write n 0x0 0xFFFFFFFF scc_flash_din3 eFlash 0 and eFlash 1 data input[127:96] 0 32 INTR_CTRL 0x50 32 read-write n 0x0 0xFFFFFFFF AZ_MPC_CFG_INIT_VALUE 0: Secure mode 1: Non-secure mode 6 7 QSPI_MPC_CFG_INIT_VALUE 0: Secure mode 1: Non-secure mode 3 4 SRAM_MPC_CFG_INIT_VALUE 0: Secure mode 1: Non-secure mode 5 6 IOMUX_ALTF1_DEFAULT_IN_0 0xA0 32 read-write n 0x0 0xFFFFFFFF iomux_altf1_default_in_0 0: Default to 0 1: Default to 1 0 32 IOMUX_ALTF1_DEFAULT_IN_1 0xA4 32 read-write n 0x0 0xFFFFFFFF iomux_altf1_default_in_1 0: Default to 0 1: Default to 1 0 6 IOMUX_ALTF1_INSEL_0 0x88 32 read-write n 0x0 0xFFFFFFFF iomux_altf1_insel_0 0: Select ATF2 1: Select ATF1 0 32 IOMUX_ALTF1_INSEL_1 0x8C 32 read-write n 0x0 0xFFFFFFFF iomux_altf1_insel_1 0: Select ATF2 1: Select ATF1 0 6 IOMUX_ALTF1_OENSEL_0 0x98 32 read-write n 0xFFFFFFFF 0xFFFFFFFF iomux_altf1_oensel_0 0: Select ATF2 1: Select ATF1 0 32 IOMUX_ALTF1_OENSEL_1 0x9C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF iomux_altf1_oensel_1 0: Select ATF2 1: Select ATF1 0 6 IOMUX_ALTF1_OUTSEL_0 0x90 32 read-write n 0xFFFFFFFF 0xFFFFFFFF iomux_altf1_outsel_0 0: Select ATF2 1: Select ATF1 0 32 IOMUX_ALTF1_OUTSEL_1 0x94 32 read-write n 0xFFFFFFFF 0xFFFFFFFF iomux_altf1_outsel_1 0: Select ATF2 1: Select ATF1 0 6 IOMUX_ALTF2_DEFAULT_IN_0 0xC0 32 read-write n 0x0 0xFFFFFFFF iomux_altf2_default_in_0 0: Default to 0 1: Default to 1 0 32 IOMUX_ALTF2_DEFAULT_IN_1 0xC4 32 read-write n 0x0 0xFFFFFFFF iomux_altf2_default_in_1 0: Default to 0 1: Default to 1 0 6 IOMUX_ALTF2_INSEL_0 0xA8 32 read-write n 0x0 0xFFFFFFFF iomux_altf2_insel_0 0: Select ATF3 1: Select ATF2 0 32 IOMUX_ALTF2_INSEL_1 0xAC 32 read-write n 0x0 0xFFFFFFFF iomux_altf2_insel_1 0: Select ATF3 1: Select ATF2 0 6 IOMUX_ALTF2_OENSEL_0 0xB8 32 read-write n 0xFFFFFFFF 0xFFFFFFFF iomux_altf2_oensel_0 0: Select ATF3 1: Select ATF2 0 32 IOMUX_ALTF2_OENSEL_1 0xBC 32 read-write n 0xFFFFFFFF 0xFFFFFFFF iomux_altf2_oensel_1 0: Select ATF3 1: Select ATF2 0 6 IOMUX_ALTF2_OUTSEL_0 0xB0 32 read-write n 0xFFFFFFFF 0xFFFFFFFF iomux_altf2_outsel_0 0: Select ATF3 1: Select ATF2 0 32 IOMUX_ALTF2_OUTSEL_1 0xB4 32 read-write n 0xFFFFFFFF 0xFFFFFFFF iomux_altf2_outsel_1 0: Select ATF3 1: Select ATF2 0 6 IOMUX_MAIN_DEFAULT_IN_0 0x80 32 read-write n 0x0 0xFFFFFFFF iomux_main_default_in_0 0: Default to 0 1: Default to 1 0 32 IOMUX_MAIN_DEFAULT_IN_1 0x84 32 read-write n 0x0 0xFFFFFFFF iomux_main_default_in_1 0: Default to 0 1: Default to 1 0 6 IOMUX_MAIN_INSEL_0 0x68 32 read-write n 0xFFFFFFFF 0xFFFFFFFF iomux_main_insel_0 0: Select ATF1 1: Select Main Function 0 32 IOMUX_MAIN_INSEL_1 0x6C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF iomux_main_insel_1 0: Select ATF1 1: Select Main Function 0 6 IOMUX_MAIN_OENSEL_0 0x78 32 read-write n 0xFFFFFFFF 0xFFFFFFFF iomux_main_oensel_0 0: Select ATF1 1: Select Main Function 0 32 IOMUX_MAIN_OENSEL_1 0x7C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF iomux_main_oensel_1 0: Select ATF1 1: Select Main Function 0 6 IOMUX_MAIN_OUTSEL_0 0x70 32 read-write n 0xFFFFFFFF 0xFFFFFFFF iomux_main_outsel_0 0: Select ATF1 1: Select Main Function 0 32 IOMUX_MAIN_OUTSEL_1 0x74 32 read-write n 0xFFFFFFFF 0xFFFFFFFF iomux_main_outsel_1 0: Select ATF1 1: Select Main Function 0 6 IOPAD_DS1_0 0xF0 32 read-write n 0xFFFFFFFF 0xFFFFFFFF drive_strength1 Most significant bits of the two-bit values that define drive strengths of test chip I/O PA31-PA0 0 32 IOPAD_DS1_1 0xF4 32 read-write n 0xFFFFFFFF 0xFFFFFFFF drive_strength_1 Most significant bits of the two-bit values that define drive strengths of test chip I/O PA37-PA32 0 6 IOPAD_DSO_0 0xE8 32 read-write n 0xFFF00000 0xFFFFFFFF drive_strength0 Least significant bits of the two-bit values that define drive strengths of test chip I/O PA31-PA0 0 32 IOPAD_DSO_1 0xEC 32 read-write n 0xFFFFFFFF 0xFFFFFFFF drive_strength_0 Least significant bits of the two-bit values that define drive strengths of test chip I/O PA37-PA32 0 6 IOPAD_IS_0 0x110 32 read-write n 0xFFFFFFFF 0xFFFFFFFF input_select Selects input mode on test chip I/O PA31-PA0 0 32 IOPAD_IS_1 0x114 32 read-write n 0xFFFFFFFF 0xFFFFFFFF input_select Selects input mode on test chip I/O PA37-PA32 0 6 IOPAD_PE_0 0xF8 32 read-write n 0xFFFFFFFF 0xFFFFFFFF pull_enable Enables pull resistors of test chip I/O PA31-PA0 0 32 IOPAD_PE_1 0xFC 32 read-write n 0xFFFFFFFF 0xFFFFFFFF pull_enable Enables pull resistors of test chip I/O PA37-PA32 0 6 IOPAD_PS_0 0x100 32 read-write n 0xFFFFFFFF 0xFFFFFFFF pull_select Enables pull resistors of test chip I/O PA31-PA0 0 32 IOPAD_PS_1 0x104 32 read-write n 0xFFFFFFFF 0xFFFFFFFF pull_select Enables pull resistors of test chip I/O PA37-PA32 0 6 IOPAD_SR_0 0x108 32 read-write n 0xFFFFFFFF 0xFFFFFFFF slew_rate Selects the slew rate of test chip I/O PA31-PA0 0 32 IOPAD_SR_1 0x10C 32 read-write n 0xFFFFFFFF 0xFFFFFFFF slew_rate Selects the slew rate of test chip I/O PA37-PA32 0 6 PLL_CTRL_MULT_PLL0_CLK 0x2C 32 read-write n 0x1388 0xFFFFFFFF pll_mult_ctrl_pll0_clk pll_mult_ctrl_pll0_clk 0 14 PLL_CTRL_PLL0_CLK 0x24 32 read-write n 0x0 0xFFFFFFFF bypass_pll0 Bypass PLL0 4 5 pd_foutpostdiv1pd Power down FOUTPOSTDIV1PD: 1 2 pd_foutpostdiv2pd Power down FOUTPOSTDIV2PD 2 3 pd_foutvcopd Power down FOUTVCOPD 3 4 pd_pll0 Power down PLL0 0 1 PLL_POSTDIV_CTRL_PLL0_CLK 0x28 32 read-write n 0x1 0xFFFFFFFF pll_postdiv_ctrl_pll0_clk pll_postdiv_ctrl_pll0_clk 0 4 PVT_CTRL 0x118 32 read-write n 0x0 0xFFFFFFFF TSTSENNUM Select PVT sensor to write to and read from 0 5 RESET_CTRL 0x40 32 read-write n 0xFFFFFFFF 0xFFFFFFFF GPIO_RESET Reset Active low 9 10 GPTIMER_RESET Reset Active low 1 2 I2C0_RESET Reset Active low 2 3 I2C1_RESET Reset Active low 3 4 I2S_RESET Reset Active low 4 5 PVT_RESET Reset Active low 10 11 PWM0_RESET Reset Active low 11 12 PWM1_RESET Reset Active low 12 13 PWM2_RESET Reset Active low 13 14 QSPI_RESET Reset Active low 6 7 RTC_RESET Reset Active low 14 15 SPI_RESET Reset Active low 5 6 UART0_RESET Reset Active low 7 8 UART1_RESET Reset Active low 8 9 SELECTION_CONTROL_REG 0x1E0 32 read-write n 0x1000200 0xFFFFFFFF clock_phase_shifter_bypass QSPI input clock phase shift control 2 3 clock_phase_shifter_select QSPI input clock phase shift control 0 2 sdio_mask_delay SDIO mask delay 8 10 SPARE0 0x130 32 read-write n 0x0 0xFFFFFFFF spare0 Spare read-write register for software 0 32 SPARE_CTRL0 0x21C 32 read-write n 0x0 0xFFFFFFFF spare_ctrl0 Spare control register 0 32 SPARE_CTRL1 0x220 32 read-write n 0x0 0xFFFFFFFF spare_ctrl1 Spare control register 0 32 SRAM_CTRL 0x4C 32 read-write n 0x48100000 0xFFFFFFFF CODE_SRAMx_PGEN SRAM cell power gate enable 0 16 SSE_OTP_RD_DATA 0x208 32 read-only n 0x0 0xFFFFFFFF sse_otp_rd_data SSE-200 OTP read data 0 32 STATIC_CONF_SIG1 0x13C 32 read-write n 0x0 0xFFFFFFFF TIHSBYPASS Cross Trigger Interface handshake bypass on CTITRIGOUT 12 16 TINIDENSEL NIDEN mask on CTITRIGINT 16 24 TISBYPASSACK Cross Trigger Interface synchronous bypass on CTITRIGOUTACK 8 12 TISBYPASSIN Cross Trigger Interface synchronous bypass on CTITRIGIN 0 8 TODBGENSEL DBGEN mask on CTITRIGOUT 24 28 SPCTRL Secure Privilege Control Block SPCTRL 0x50080000 0x0 0x1000 registers n AHBNSPPC0 Non-Secure Access AHB slave Peripheral Protection Control 0 0x50 32 read-write n 0x0 0xFFFFFFFF AHBNSPPCEXP0 Expansion 0 Non_Secure Access AHB slave Peripheral Protection Control 0x60 32 read-write n 0x0 0xFFFFFFFF AHBNSPPCEXP1 Expansion 1 Non_Secure Access AHB slave Peripheral Protection Control 0x64 32 read-write n 0x0 0xFFFFFFFF AHBNSPPCEXP2 Expansion 2 Non_Secure Access AHB slave Peripheral Protection Control 0x68 32 read-write n 0x0 0xFFFFFFFF AHBNSPPCEXP3 Expansion 3 Non_Secure Access AHB slave Peripheral Protection Control 0x6C 32 read-write n 0x0 0xFFFFFFFF AHBSPPPC0 Secure Unprivileged Access AHB slave Peripheral Protection Control 0 0x90 32 read-only n 0x0 0xFFFFFFFF AHBSPPPCEXP0 Expansion 0 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA0 32 read-write n 0x0 0xFFFFFFFF AHBSPPPCEXP1 Expansion 1 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA4 32 read-write n 0x0 0xFFFFFFFF AHBSPPPCEXP2 Expansion 2 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA8 32 read-write n 0x0 0xFFFFFFFF AHBSPPPCEXP3 Expansion 3 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xAC 32 read-write n 0x0 0xFFFFFFFF APBNSPPC0 Non-Secure Access APB slave Peripheral Protection Control 0 0x70 32 read-write n 0x0 0xFFFFFFFF APBNSPPC1 Non-Secure Access APB slave Peripheral Protection Control 1 0x74 32 read-write n 0x0 0xFFFFFFFF APBNSPPCEXP0 Expansion 0 Non_Secure Access APB slave Peripheral Protection Control 0x80 32 read-write n 0x0 0xFFFFFFFF APBNSPPCEXP1 Expansion 1 Non_Secure Access APB slave Peripheral Protection Control 0x84 32 read-write n 0x0 0xFFFFFFFF APBNSPPCEXP2 Expansion 2 Non_Secure Access APB slave Peripheral Protection Control 0x88 32 read-write n 0x0 0xFFFFFFFF APBNSPPCEXP3 Expansion 3 Non_Secure Access APB slave Peripheral Protection Control 0x8C 32 read-write n 0x0 0xFFFFFFFF APBSPPPC0 Secure Unprivileged Access APB slave Peripheral Protection Control 0 0xB0 32 read-write n 0x0 0xFFFFFFFF APBSPPPC1 Secure Unprivileged Access APB slave Peripheral Protection Control 1 0xB4 32 read-write n 0x0 0xFFFFFFFF APBSPPPCEXP0 Expansion 0 Secure Unprivileged Access APB slave Peripheral Protection Control 0xC0 32 read-write n 0x0 0xFFFFFFFF APBSPPPCEXP1 Expansion 1 Secure Unprivileged Access APB slave Peripheral Protection Control 0xC4 32 read-write n 0x0 0xFFFFFFFF APBSPPPCEXP2 Expansion 2 Secure Unprivileged Access APB slave Peripheral Protection Control 0xC8 32 read-write n 0x0 0xFFFFFFFF APBSPPPCEXP3 Expansion 3 Secure Unprivileged Access APB slave Peripheral Protection Control 0xCC 32 read-write n 0x0 0xFFFFFFFF BRGINTCLR Bridge Buffer Error Interrupt Clear 0x44 32 write-only n 0x0 0xFFFFFFFF BRGINTEN Bridge Buffer Error Interrupt Enable 0x48 32 read-write n 0x0 0xFFFFFFFF BRGINTSTAT Bridge Buffer Error Interrupt Status 0x40 32 read-only n 0x0 0xFFFFFFFF BUSWAIT Bus Access wait control after reset 0x4 32 read-write n 0x0 0xFFFFFFFF CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF NSCCFG Non Secure Callable Configuration for IDAU 0x14 32 read-write n 0x0 0xFFFFFFFF NSMSCEXP Expansion MSC Non-Secure Configuration 0xD0 32 read-only n 0x0 0xFFFFFFFF PID0 Peripheral ID 0 0xFE0 32 read-only n 0x52 0xFFFFFFFF PID1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PID2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF PID3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF PID4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF SECMPCINTSTATUS Secure MPC Interrupt Status 0x1C 32 read-only n 0x0 0xFFFFFFFF SECMSCINTCLR Secure MSC Interrupt Clear 0x34 32 read-write n 0x0 0xFFFFFFFF SECMSCINTEN Secure MSC Interrupt Enable 0x38 32 read-write n 0x0 0xFFFFFFFF SECMSCINTSTAT Secure MSC Interrupt Status 0x30 32 read-only n 0x0 0xFFFFFFFF SECPPCINTCLR Secure PPC Interrupt Clear 0x24 32 write-only n 0x0 0xFFFFFFFF SECPPCINTEN Secure PPC Interrupt Enable 0x28 32 read-write n 0x0 0xFFFFFFFF SECPPCINTSTAT Secure PPC Interrupt Status 0x20 32 read-only n 0x0 0xFFFFFFFF SECRESPCFG Security Violation Response Configuration register 0x10 32 read-write n 0x0 0xFFFFFFFF SPCSECTRL Secure Privilege Controller Secure Configuration Control register 0x0 32 read-write n 0x0 0xFFFFFFFF SPI0 SPI 0 SPI 0x4010A000 0x0 0xFC registers n SPIINTR0 SPI0 interrupt 37 SPICR Control register 0x0 read-write n 0x20000 0xFFFFFFFF CPHA Clock Phase: Selects whether the SPI clock is in active or inactive phase outside the SPI word 2 1 CPOL External Clock Edge: Selects the SPI clock polarity outside SPI word 1 1 MBRD Master Baud Rate Divisor (2 to 256). The SCLK is generated base on SPI REFERENCE CLOCK or ext_clk divided by MBRD 3 3 MCSE Manual Chip Select Enable: When this bit is set, the n_ss_out[3:0] lines will be driven permanently by the encoded peripheral select value regardless of the current state of the main SPI state machine 14 1 MFGE Mode Fail Generation Enable: When this bit is set the logic generating Mode Fail is enabled 17 1 MRCS Reference Clock Select: When this bit is set the ext_clk is used, otherwise SPI REFERENCE CLOCK is used 8 1 MSC Manual Start Command: When manual start mode is enabled (see Manual Start Enable bit of Configuration Register) and TX FIFO is not empty, writing a ‘1’ to this bit will start transmission. Writing a '0' will have no effect. It returns ‘0’ when read 16 1 MSE Manual Start Enable: When this bit is set do not allow transmission to start until Manual Start Command (see MSC) bit is written with a '1' 15 1 MSEL Mode Select: Selects SPI controller mode (MASTER/SLAVE) 0 1 PCSL Peripheral Chip Select Lines (master mode only): When Peripheral Select Decode is set then PCSL[3:0] directly drives n_ss_out [3:0], else (PSD is written with ‘0’) PCSL[3:0] drives n_ss_out [3:0] 10 4 PSD Peripheral Select Decode: When this bit is set allow external 4-to-16 decode (n_ss_out [3:0 = PCSL [3:0]). When Peripheral Select Decode is not set, only 1 of 4 selects n_ss_out[3:0] are active (see PCSL) 9 1 RXCLR RX FIFO Clear: Writing a ‘1’ to this bit will clear the RX FIFO. Writing a '0' will have no effect. It returns ‘0’ when read 19 1 SPSE Sample Point Shift Enable: When this bit is set and controller is in MASTER receiver mode then sample point of receiving data is shifted with respect to sample point of SPI protocol specification 18 1 TWS Transfer Word Size: Define size of word to be transferred. This MUST be equal to the FIFO width (FF_W), or a sub-multiple of FF_W to allow multiple word transfers per FIFO word 6 2 TXCLR TX FIFO Clear: Writing a ‘1’ to this bit will clear the TX FIFO. Writing a '0' will have no effect. It returns ‘0’ when read 20 1 SPIENR SPI Enable Register 0x14 read-write n 0x0 0xFFFFFFFF SPIE SPI Enable: When this bit is set the SPI controller is enabled, otherwise SPI is disabled. When SPI controller is disabled all output enables are inactive and all pins are set to input mode. Writing ‘0’ disables the SPI controller once current transfer of the data word (FF_W) is complete 0 1 SPIIDR Interrupt Disable Register 0xC -1 write-only n 0x0 0xFFFFFFFF MFD Mode Fail Disable 1 1 RFD RX FIFO Full Disable 5 1 RNED RX FIFO Not Empty Disable 4 1 ROFD RX FIFO Overflow Disable 0 1 TFD TX FIFO Full Disable 3 1 TNFD TX FIFO Not Full Disable 2 1 TUFD TX FIFO Underflow Disable 6 1 SPIIER Interrupt Enable Register 0x8 -1 write-only n 0x0 0xFFFFFFFF MFE Mode Fail Enable 1 1 RFE RX FIFO Full Enable 5 1 RNEE RX FIFO Not Empty Enable 4 1 ROFE RX FIFO Overflow Enable 0 1 TFE TX FIFO Full Enable 3 1 TNFE TX FIFO Not Full Enable 2 1 TUFE TX FIFO Underflow Enable 6 1 SPIIMR Interrupt Mask Register 0x10 -1 read-only n 0x0 0xFFFFFFFF MFM Mode Fail Mask 1 1 RFM RX FIFO Full Mask 5 1 RNEM RX FIFO Not Empty Mask 4 1 ROFM RX FIFO Overflow Mask 0 1 TFM TX FIFO Full Mask 3 1 TNFM TX FIFO Not Full Mask 2 1 TUFM TX FIFO Underflow Mask 6 1 SPIISR Interrupt Status Register 0x4 -1 read-only n 0x4 0xFFFFFFFF MF Mode Fail: Indicates the voltage on pin n_ss_in is inconsistent with the SPI mode 1 1 RF RX FIFO Full (current FIFO status) 5 1 RNE RX FIFO Not Empty (current FIFO status) 4 1 ROF RX FIFO Overflow: This bit is set if an attempt is made to push the RX FIFO when it is full 0 1 TF TX FIFO Full (current FIFO status) 3 1 TNF TX FIFO Not Full (current FIFO status) 2 1 TUF TX FIFO Underflow: This bit is reset only by a system reset and cleared only when the register is read 6 1 SPIRDR Receive Data Register 0x20 -1 read-only n 0x0 0xFFFFFFFF RDATA Receive Data: Reads the RX FIFO location indicated by the current read address and then increments the read address 0 8 SPITDR Transmit Data Register 0x1C -1 write-only n 0x0 0xFFFFFFFF TDATA Transmit Data: Writes to the TX FIFO location indicated by its internal write address and increments the write address by pushing it 0 8 SPI0_Secure SPI0 (Secure) SPI 0x5010A000 0x0 0xFC registers n SPICR Control register 0x0 read-write n 0x20000 0xFFFFFFFF CPHA Clock Phase: Selects whether the SPI clock is in active or inactive phase outside the SPI word 2 1 CPOL External Clock Edge: Selects the SPI clock polarity outside SPI word 1 1 MBRD Master Baud Rate Divisor (2 to 256). The SCLK is generated base on SPI REFERENCE CLOCK or ext_clk divided by MBRD 3 3 MCSE Manual Chip Select Enable: When this bit is set, the n_ss_out[3:0] lines will be driven permanently by the encoded peripheral select value regardless of the current state of the main SPI state machine 14 1 MFGE Mode Fail Generation Enable: When this bit is set the logic generating Mode Fail is enabled 17 1 MRCS Reference Clock Select: When this bit is set the ext_clk is used, otherwise SPI REFERENCE CLOCK is used 8 1 MSC Manual Start Command: When manual start mode is enabled (see Manual Start Enable bit of Configuration Register) and TX FIFO is not empty, writing a ‘1’ to this bit will start transmission. Writing a '0' will have no effect. It returns ‘0’ when read 16 1 MSE Manual Start Enable: When this bit is set do not allow transmission to start until Manual Start Command (see MSC) bit is written with a '1' 15 1 MSEL Mode Select: Selects SPI controller mode (MASTER/SLAVE) 0 1 PCSL Peripheral Chip Select Lines (master mode only): When Peripheral Select Decode is set then PCSL[3:0] directly drives n_ss_out [3:0], else (PSD is written with ‘0’) PCSL[3:0] drives n_ss_out [3:0] 10 4 PSD Peripheral Select Decode: When this bit is set allow external 4-to-16 decode (n_ss_out [3:0 = PCSL [3:0]). When Peripheral Select Decode is not set, only 1 of 4 selects n_ss_out[3:0] are active (see PCSL) 9 1 RXCLR RX FIFO Clear: Writing a ‘1’ to this bit will clear the RX FIFO. Writing a '0' will have no effect. It returns ‘0’ when read 19 1 SPSE Sample Point Shift Enable: When this bit is set and controller is in MASTER receiver mode then sample point of receiving data is shifted with respect to sample point of SPI protocol specification 18 1 TWS Transfer Word Size: Define size of word to be transferred. This MUST be equal to the FIFO width (FF_W), or a sub-multiple of FF_W to allow multiple word transfers per FIFO word 6 2 TXCLR TX FIFO Clear: Writing a ‘1’ to this bit will clear the TX FIFO. Writing a '0' will have no effect. It returns ‘0’ when read 20 1 SPIENR SPI Enable Register 0x14 read-write n 0x0 0xFFFFFFFF SPIE SPI Enable: When this bit is set the SPI controller is enabled, otherwise SPI is disabled. When SPI controller is disabled all output enables are inactive and all pins are set to input mode. Writing ‘0’ disables the SPI controller once current transfer of the data word (FF_W) is complete 0 1 SPIIDR Interrupt Disable Register 0xC -1 write-only n 0x0 0xFFFFFFFF MFD Mode Fail Disable 1 1 RFD RX FIFO Full Disable 5 1 RNED RX FIFO Not Empty Disable 4 1 ROFD RX FIFO Overflow Disable 0 1 TFD TX FIFO Full Disable 3 1 TNFD TX FIFO Not Full Disable 2 1 TUFD TX FIFO Underflow Disable 6 1 SPIIER Interrupt Enable Register 0x8 -1 write-only n 0x0 0xFFFFFFFF MFE Mode Fail Enable 1 1 RFE RX FIFO Full Enable 5 1 RNEE RX FIFO Not Empty Enable 4 1 ROFE RX FIFO Overflow Enable 0 1 TFE TX FIFO Full Enable 3 1 TNFE TX FIFO Not Full Enable 2 1 TUFE TX FIFO Underflow Enable 6 1 SPIIMR Interrupt Mask Register 0x10 -1 read-only n 0x0 0xFFFFFFFF MFM Mode Fail Mask 1 1 RFM RX FIFO Full Mask 5 1 RNEM RX FIFO Not Empty Mask 4 1 ROFM RX FIFO Overflow Mask 0 1 TFM TX FIFO Full Mask 3 1 TNFM TX FIFO Not Full Mask 2 1 TUFM TX FIFO Underflow Mask 6 1 SPIISR Interrupt Status Register 0x4 -1 read-only n 0x4 0xFFFFFFFF MF Mode Fail: Indicates the voltage on pin n_ss_in is inconsistent with the SPI mode 1 1 RF RX FIFO Full (current FIFO status) 5 1 RNE RX FIFO Not Empty (current FIFO status) 4 1 ROF RX FIFO Overflow: This bit is set if an attempt is made to push the RX FIFO when it is full 0 1 TF TX FIFO Full (current FIFO status) 3 1 TNF TX FIFO Not Full (current FIFO status) 2 1 TUF TX FIFO Underflow: This bit is reset only by a system reset and cleared only when the register is read 6 1 SPIRDR Receive Data Register 0x20 -1 read-only n 0x0 0xFFFFFFFF RDATA Receive Data: Reads the RX FIFO location indicated by the current read address and then increments the read address 0 8 SPITDR Transmit Data Register 0x1C -1 write-only n 0x0 0xFFFFFFFF TDATA Transmit Data: Writes to the TX FIFO location indicated by its internal write address and increments the write address by pushing it 0 8 SRAM0MPC Memory Protection Controller 0 SRAM_MPC 0x50083000 0x0 0x1000 registers n MPC MPC Combined 9 BLK_CFG Block Configuration 0x14 32 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 32 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C 32 read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index register 0x10 32 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 1 bit[3_0] Block size 0 4 CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF CTRL MPC Control register 0x0 32 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 1 bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 INT_CLEAR Interrupt clear 0x24 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 32 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 32 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x60 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Peripheral ID 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF SRAM1MPC SRAM 1 Memory Protection Controller SRAM_MPC 0x50084000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 32 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 32 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C 32 read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index register 0x10 32 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 1 bit[3_0] Block size 0 4 CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF CTRL MPC Control register 0x0 32 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 1 bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 INT_CLEAR Interrupt clear 0x24 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 32 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 32 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x60 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Peripheral ID 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF SRAM2MPC SRAM 2 Memory Protection Controller SRAM_MPC 0x50085000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 32 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 32 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C 32 read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index register 0x10 32 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 1 bit[3_0] Block size 0 4 CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF CTRL MPC Control register 0x0 32 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 1 bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 INT_CLEAR Interrupt clear 0x24 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 32 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 32 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x60 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Peripheral ID 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF SRAM3MPC SRAM 3 Memory Protection Controller SRAM_MPC 0x50086000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 32 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 32 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C 32 read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index register 0x10 32 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 1 bit[3_0] Block size 0 4 CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF CTRL MPC Control register 0x0 32 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 1 bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 INT_CLEAR Interrupt clear 0x24 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 32 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 32 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x60 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Peripheral ID 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF SYSINFO System Information SYSINFO 0x40020000 0x0 0x1000 registers n CIDR0 Component ID 0 0xFF0 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC read-only n 0xB1 0xFFFFFFFF PIDR0 Peripheral ID 0 0xFE0 read-only n 0x58 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 read-only n 0xB 0xFFFFFFFF PIDR3 Peripheral ID 3 0xFEC read-only n 0x0 0xFFFFFFFF PIDR4 Peripheral ID 4 0xFD0 read-only n 0x4 0xFFFFFFFF SYS_CONFIG System Hardware Configuration register 0x4 read-only n 0x0 0xFFFFFFFF CPU0_HAS_TCM CPU 0 has Data TCM: 9 10 No CPU 0 does not have Data TCM 0 Yes CPU 0 has Data TCM 1 CPU0_TCM_BANK_NUM The SRAM Bank that maps CPU0 Data TCM 16 20 CPU0_TYPE CPU 0 Core Type 24 28 Not Exist Does Not Exist 0x0 CM33 Cortex-M33 Core 0x2 CPU1_HAS_TCM CPU 1 has Data TCM: 10 11 No CPU 1 does not have Data TCM 0 Yes CPU 1 has Data TCM 1 CPU1_TCM_BANK_NUM Number of SRAM banks 20 24 Otherwise Otherwise 0x0 Two 2 SRAM Banks 0x1 Three 3 SRAM Banks 0x2 Four 4 SRAM Banks 0x3 CPU1_TYPE CPU 1 Core Type 28 32 Not Exist Does Not Exist 0x0 CM33 Cortex-M33 Core 0x2 HAS_CRYPTO Whether CryptoCell Included: 12 13 No CryptoCell Not Included 0 Yes CryptoCell Included 1 SRAM_ADDR_WIDTH SRAM Bank Address Width 4 9 SRAM_NUM_BANK SRAM Number of Banks 0 4 SYS_VERSION System Version Register 0x0 read-only n 0x22041743 0xFFFFFFFF CONFIGURATION CONFIGURATION for SSE-200 r2: 0x2 28 32 DESIGNER_ID Arm Product with designer code 0x41 12 20 MAJOR_REVISION Major Revision 24 28 MINOR_REVISION Minor Revision 20 24 PART_NUMBER Part Number for the SSE-200 0 12 SYSINFO_Secure System Information (Secure) SYSINFO 0x50020000 0x0 0x1000 registers n CIDR0 Component ID 0 0xFF0 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC read-only n 0xB1 0xFFFFFFFF PIDR0 Peripheral ID 0 0xFE0 read-only n 0x58 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 read-only n 0xB 0xFFFFFFFF PIDR3 Peripheral ID 3 0xFEC read-only n 0x0 0xFFFFFFFF PIDR4 Peripheral ID 4 0xFD0 read-only n 0x4 0xFFFFFFFF SYS_CONFIG System Hardware Configuration register 0x4 read-only n 0x0 0xFFFFFFFF CPU0_HAS_TCM CPU 0 has Data TCM: 9 10 No CPU 0 does not have Data TCM 0 Yes CPU 0 has Data TCM 1 CPU0_TCM_BANK_NUM The SRAM Bank that maps CPU0 Data TCM 16 20 CPU0_TYPE CPU 0 Core Type 24 28 Not Exist Does Not Exist 0x0 CM33 Cortex-M33 Core 0x2 CPU1_HAS_TCM CPU 1 has Data TCM: 10 11 No CPU 1 does not have Data TCM 0 Yes CPU 1 has Data TCM 1 CPU1_TCM_BANK_NUM Number of SRAM banks 20 24 Otherwise Otherwise 0x0 Two 2 SRAM Banks 0x1 Three 3 SRAM Banks 0x2 Four 4 SRAM Banks 0x3 CPU1_TYPE CPU 1 Core Type 28 32 Not Exist Does Not Exist 0x0 CM33 Cortex-M33 Core 0x2 HAS_CRYPTO Whether CryptoCell Included: 12 13 No CryptoCell Not Included 0 Yes CryptoCell Included 1 SRAM_ADDR_WIDTH SRAM Bank Address Width 4 9 SRAM_NUM_BANK SRAM Number of Banks 0 4 SYS_VERSION System Version Register 0x0 read-only n 0x22041743 0xFFFFFFFF CONFIGURATION CONFIGURATION for SSE-200 r2: 0x2 28 32 DESIGNER_ID Arm Product with designer code 0x41 12 20 MAJOR_REVISION Major Revision 24 28 MINOR_REVISION Minor Revision 20 24 PART_NUMBER Part Number for the SSE-200 0 12 SystemControl System Control SYSCTRL 0x50021000 0x0 0x1000 registers n CIDR0 Component ID 0 0xFF0 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC read-only n 0xB1 0xFFFFFFFF CLOCK_FORCE Clock Force 0x18 read-write n 0x0 0xFFFFFFFF CPUFCLK_FORCE Force all CPU FCLK to run when set to HIGH 6 7 CPUSYSCLK_FORCE Force all CPU SYSCLK to run when set to HIGH 5 6 CRYPTOSYSCLK_FORCE Force all CryptoCell clocks to run when set to HIGH 7 8 FCLKHINTGATE_ENABLE Enable FCLK gating by HINTSYSCLKEN when CPU 1 is OFF 8 9 latency improve SRAM3 access latency at the cost of increased power consumption 0 enable Enable FCLK gating by HINTSYSCLKEN when CPU 1 is OFF 1 MAINCLK_FORCE Force MAINCLK to run when set to HIGH 0 1 SRAMFCLK_FORCE Force SRAM Local FCLK to run when set to HIGH 4 5 SRAMSYSCLK_FORCE Force SRAM Local SYSCLK to run when set to HIGH 3 4 SYSFCLK_FORCE Force Base element Local FCLK to run when set to HIGH 2 3 SYSSYSCLK_FORCE Force Base element Local SYSCLK to run when set to HIGH 1 2 CPUWAIT CPU Boot wait control after reset 0x118 read-write n 0x0 0xFFFFFFFF CPU0WAIT CPU 0 waits at boot and whether CPU1 powers up 0 1 read-write normally or power-up CPU0 boot normally. From Power ON reset, nSRST reset or Watchdog Reset, CPU 1 powers up 0 wait or no power-up CPU0 wait. From Power ON reset, nSRST reset or Watchdog Reset, CPU 1 do not power up 1 CPU1WAIT CPU 1 waits at boot and whether CPU0 powers up 1 2 read-write normally or power-up CPU1 boot normally. From Power ON reset, nSRST reset or Watchdog Reset, CPU 0 powers up 0 wait or no power-up CPU1 wait. From Power ON reset, nSRST reset or Watchdog Reset, CPU 0 do not power up 1 EWCTRL External Wakeup Control 0x124 read-write n 0x0 0xFFFFFFFF EWC0EN_CLR High Active External Wakeup Controller 0 Clear 8 9 write-only EWC0EN_SET EHigh Active External Wakeup Controller 0 Set 4 5 write-only EWC0EN_STATUS External Wakeup Controller 0 Enable 0 1 read-only disabled External Wakeup Controller 0 Disabled 0 enable External Wakeup Controller 0 Enabled 1 EWC1EN_CLR High Active External Wakeup Controller 1 Clear 9 10 write-only EWC1EN_SET High Active External Wakeup Controller 1 Set 5 6 write-only EWC1EN_STATUS External Wakeup Controller 1 Enable 1 2 read-only disabled External Wakeup Controller 1 Disabled 0 enable External Wakeup Controller 1 Enabled 1 FCLK_DIV Fast Clock Divider Configuration 0x10 read-write n 0x0 0xFFFFFFFF FCLKDIV FCLK from MAINCLK Clock Divider Ratio Request 0 5 FCLKDIV_CUR Clock Divider Current Value. 16 21 read-only GRETREG General Purpose Retention 0x10C read-write n 0x0 0xFFFFFFFF GRETREG General Purpose Retention Register 0 16 read-write INITSVRTOR0 Initial Secure Reset Vector Register For CPU 0 0x110 read-write n 0x0 0xFFFFFFFF INITSVTOR0 Default Secure Vector table offset at reset for CPU 0 7 32 read-write INITSVRTOR1 Initial Secure Reset Vector Register For CPU 1 0x114 read-write n 0x0 0xFFFFFFFF INITSVTOR1 Default Secure Vector table offset at reset for CPU 1 7 32 read-write NMI_ENABLE NMI Enable Register 0x11C read-write n 0x0 0xFFFFFFFF CPU0_EXPNMI_ENABLE CPU0 Externally Sourced NMI Enable 16 17 read-write disabled CPU0 Externally Sourced NMI Disabled 0 enable CPU0 Externally Sourced NMI Enabled 1 CPU0_INTNMI_ENABLE CPU0 Internally Sourced NMI Enable 0 1 read-write disabled CPU0 Internally Sourced NMI Disabled 0 enable CPU0 Internally Sourced NMI Enabled 1 CPU1_EXPNMI_ENABLE CPU1 Externally Sourced NMI Enable 17 18 read-write disabled CPU1 Externally Sourced NMI Disabled 0 enable CPU1 Externally Sourced NMI Enabled 1 CPU1_INTNMI_ENABLE CPU1 Internally Sourced NMI Enable 1 2 read-write disabled CPU1 Internally Sourced NMI Disabled 0 enable CPU1 Internally Sourced NMI Enabled 1 PDCM_PD_SRAM0_SENSE Power Control Depedendency Matrix PD_SRAM0 Power Domain Sensitivity 0x20C read-write n 0x0 0xFFFFFFFF S_PD_CPU0CORE_ON Enable sensitivity to PD_CPU0CORE 1 2 read-write disable Disable sensitivity to PD_CPU0CORE 0 enable Enable sensitivity to PD_CPU0CORE 1 S_PD_CPU1CORE_ON Enable sensitivity to PD_CPU1CORE 2 3 read-write disable Disable sensitivity to PD_CPU1CORE 0 enable Enable sensitivity to PD_CPU1CORE 1 S_PD_CRYPTO_ON Tied LOW 12 13 read-only Low Ignores PD_CRYPTO 0 S_PD_EXP0_IN Enable PDEXPIN[0] signal Sensitivity 16 17 read-write disable Disable PDEXPIN[0] signal Sensitivity 0 enable Enable PDEXPIN[0] signal Sensitivity 1 S_PD_EXP1_IN Enable PDEXPIN[1] signal Sensitivity 17 18 read-write disable Disable PDEXPIN[1] signal Sensitivity 0 enable Enable PDEXPIN[1] signal Sensitivity 1 S_PD_EXP2_IN Enable PDEXPIN[2] signal Sensitivity 18 19 read-write disable Disable PDEXPIN[2] signal Sensitivity 0 enable Enable PDEXPIN[2] signal Sensitivity 1 S_PD_EXP3_IN Enable PDEXPIN[3] signal Sensitivity 19 20 read-write disable Disable PDEXPIN[3] signal Sensitivity 0 enable Enable PDEXPIN[3] signal Sensitivity 1 S_PD_SRAM0_ON Enable sensitivity to PD_SRAM0 3 4 read-write disable Disable sensitivity to PD_SRAM0 0 enable Enable sensitivity to PD_SRAM0 1 S_PD_SRAM1_ON Tied LOW 4 5 read-only Low Ignores PD_SRAM1 state 0 S_PD_SRAM2_ON Tied LOW 5 6 read-only Low Ignores PD_SRAM2 state 0 S_PD_SRAM3_ON Tied LOW 6 7 read-only Low Ignores PD_SRAM3 state 0 S_PD_SYS_ON Enable sensitivity to PD_SYS 0 1 read-write disable Disable sensitivity to PD_SYS 0 enable Enable sensitivity to PD_SYS 1 PDCM_PD_SRAM1_SENSE Power Control Depedendency Matrix PD_SRAM1 Power Domain Sensitivity 0x210 read-write n 0x0 0xFFFFFFFF S_PD_CPU0CORE_ON Enable sensitivity to PD_CPU0CORE 1 2 read-write disable Disable sensitivity to PD_CPU0CORE 0 enable Enable sensitivity to PD_CPU0CORE 1 S_PD_CPU1CORE_ON Enable sensitivity to PD_CPU1CORE 2 3 read-write disable Disable sensitivity to PD_CPU1CORE 0 enable Enable sensitivity to PD_CPU1CORE 1 S_PD_CRYPTO_ON Tied LOW 12 13 read-only Low Ignores PD_CRYPTO 0 S_PD_EXP0_IN Enable PDEXPIN[0] signal Sensitivity 16 17 read-write disable Disable PDEXPIN[0] signal Sensitivity 0 enable Enable PDEXPIN[0] signal Sensitivity 1 S_PD_EXP1_IN Enable PDEXPIN[1] signal Sensitivity 17 18 read-write disable Disable PDEXPIN[1] signal Sensitivity 0 enable Enable PDEXPIN[1] signal Sensitivity 1 S_PD_EXP2_IN Enable PDEXPIN[2] signal Sensitivity 18 19 read-write disable Disable PDEXPIN[2] signal Sensitivity 0 enable Enable PDEXPIN[2] signal Sensitivity 1 S_PD_EXP3_IN Enable PDEXPIN[3] signal Sensitivity 19 20 read-write disable Disable PDEXPIN[3] signal Sensitivity 0 enable Enable PDEXPIN[3] signal Sensitivity 1 S_PD_SRAM0_ON Tied LOW 3 4 read-only Low Ignores PD_SRAM0 state 0 S_PD_SRAM1_ON Enable sensitivity to PD_SRAM1 4 5 read-write disable Disable sensitivity to PD_SRAM1 0 enable Enable sensitivity to PD_SRAM1 1 S_PD_SRAM2_ON Tied LOW 5 6 read-only Low Ignores PD_SRAM2 state 0 S_PD_SRAM3_ON Tied LOW 6 7 read-only Low Ignores PD_SRAM3 state 0 S_PD_SYS_ON Enable sensitivity to PD_SYS 0 1 read-write disable Disable sensitivity to PD_SYS 0 enable Enable sensitivity to PD_SYS 1 PDCM_PD_SRAM2_SENSE Power Control Depedendency Matrix PD_SRAM2 Power Domain Sensitivity 0x214 read-write n 0x0 0xFFFFFFFF S_PD_CPU0CORE_ON Enable sensitivity to PD_CPU0CORE 1 2 read-write disable Disable sensitivity to PD_CPU0CORE 0 enable Enable sensitivity to PD_CPU0CORE 1 S_PD_CPU1CORE_ON Enable sensitivity to PD_CPU1CORE 2 3 read-write disable Disable sensitivity to PD_CPU1CORE 0 enable Enable sensitivity to PD_CPU1CORE 1 S_PD_CRYPTO_ON Tied LOW 12 13 read-only Low Ignores PD_CRYPTO 0 S_PD_EXP0_IN Enable PDEXPIN[0] signal Sensitivity 16 17 read-write disable Disable PDEXPIN[0] signal Sensitivity 0 enable Enable PDEXPIN[0] signal Sensitivity 1 S_PD_EXP1_IN Enable PDEXPIN[1] signal Sensitivity 17 18 read-write disable Disable PDEXPIN[1] signal Sensitivity 0 enable Enable PDEXPIN[1] signal Sensitivity 1 S_PD_EXP2_IN Enable PDEXPIN[2] signal Sensitivity 18 19 read-write disable Disable PDEXPIN[2] signal Sensitivity 0 enable Enable PDEXPIN[2] signal Sensitivity 1 S_PD_EXP3_IN Enable PDEXPIN[3] signal Sensitivity 19 20 read-write disable Disable PDEXPIN[3] signal Sensitivity 0 enable Enable PDEXPIN[3] signal Sensitivity 1 S_PD_SRAM0_ON Tied LOW 3 4 read-only Low Ignores PD_SRAM0 state 0 S_PD_SRAM1_ON Tied LOW 4 5 read-only Low Ignores PD_SRAM1 state 0 S_PD_SRAM2_ON Enable sensitivity to PD_SRAM2 5 6 read-write disable Disable sensitivity to PD_SRAM2 0 enable Enable sensitivity to PD_SRAM2 1 S_PD_SRAM3_ON Tied LOW 6 7 read-only Low Ignores PD_SRAM3 state 0 S_PD_SYS_ON Enable sensitivity to PD_SYS 0 1 read-write disable Disable sensitivity to PD_SYS 0 enable Enable sensitivity to PD_SYS 1 PDCM_PD_SRAM3_SENSE Power Control Depedendency Matrix PD_SRAM3 Power Domain Sensitivity 0x218 read-write n 0x0 0xFFFFFFFF S_PD_CPU0CORE_ON Enable sensitivity to PD_CPU0CORE 1 2 read-write disable Disable sensitivity to PD_CPU0CORE 0 enable Enable sensitivity to PD_CPU0CORE 1 S_PD_CPU1CORE_ON Enable sensitivity to PD_CPU1CORE 2 3 read-write disable Disable sensitivity to PD_CPU1CORE 0 enable Enable sensitivity to PD_CPU1CORE 1 S_PD_CRYPTO_ON Tied LOW 12 13 read-only Low Ignores PD_CRYPTO 0 S_PD_EXP0_IN Enable PDEXPIN[0] signal Sensitivity 16 17 read-write disable Disable PDEXPIN[0] signal Sensitivity 0 enable Enable PDEXPIN[0] signal Sensitivity 1 S_PD_EXP1_IN Enable PDEXPIN[1] signal Sensitivity 17 18 read-write disable Disable PDEXPIN[1] signal Sensitivity 0 enable Enable PDEXPIN[1] signal Sensitivity 1 S_PD_EXP2_IN Enable PDEXPIN[2] signal Sensitivity 18 19 read-write disable Disable PDEXPIN[2] signal Sensitivity 0 enable Enable PDEXPIN[2] signal Sensitivity 1 S_PD_EXP3_IN Enable PDEXPIN[3] signal Sensitivity 19 20 read-write disable Disable PDEXPIN[3] signal Sensitivity 0 enable Enable PDEXPIN[3] signal Sensitivity 1 S_PD_SRAM0_ON Tied LOW 3 4 read-only Low Ignores PD_SRAM0 state 0 S_PD_SRAM1_ON Tied LOW 4 5 read-only Low Ignores PD_SRAM1 state 0 S_PD_SRAM2_ON Tied LOW 5 6 read-only Low Ignores PD_SRAM2 state 0 S_PD_SRAM3_ON Enable sensitivity to PD_SRAM3 6 7 read-write disable Disable sensitivity to PD_SRAM3 0 enable Enable sensitivity to PD_SRAM3 1 S_PD_SYS_ON Enable sensitivity to PD_SYS 0 1 read-write disable Disable sensitivity to PD_SYS 0 enable Enable sensitivity to PD_SYS 1 PDCM_PD_SYS_SENSE External Wakeup Control 0x200 read-write n 0x7F 0xFFFFFFFF S_PD_CPU0CORE_ON Tied to HIGH 1 2 read-only high PD_SYS always tries to stay ON if PD_CPU0CORE is ON 1 S_PD_CPU1CORE_ON Tied to HIGH 2 3 read-only high PD_SYS always tries to stay ON if PD_CPU1CORE is ON 1 S_PD_CRYPTO_ON Tied to HIGH 12 13 read-only high PD_SYS always tries to keep ON if S_PD_CRYPTO_ON is ON 1 S_PD_EXP0_IN Enable PDEXPIN[0] signal Sensitivity 16 17 read-write disabled Disable PDEXPIN[0] signal Sensitivity. 0 enable Enable PDEXPIN[0] signal Sensitivity. 1 S_PD_EXP1_IN Enable PDEXPIN[1] signal Sensitivity 17 18 read-write disabled Disable PDEXPIN[1] signal Sensitivity. 0 enable Enable PDEXPIN[1] signal Sensitivity. 1 S_PD_EXP2_IN Enable PDEXPIN[2] signal Sensitivity 18 19 read-write disabled Disable PDEXPIN[2] signal Sensitivity. 0 enable Enable PDEXPIN[2] signal Sensitivity. 1 S_PD_EXP3_IN Enable PDEXPIN[3] signal Sensitivity 19 20 read-write disabled Disable PDEXPIN[3] signal Sensitivity. 0 enable Enable PDEXPIN[3] signal Sensitivity. 1 S_PD_SRAM0_ON Tied to HIGH 3 4 read-only high PD_SYS always tries to keep ON if SRAM0 power domain is ON 1 S_PD_SRAM1_ON Tied to HIGH 4 5 read-only high PD_SYS always tries to keep ON if SRAM1 power domain is ON 1 S_PD_SRAM2_ON Tied to HIGH 5 6 read-only high PD_SYS always tries to keep ON if SRAM2 power domain is ON 1 S_PD_SRAM3_ON Tied to HIGH 6 7 read-only high PD_SYS always tries to keep ON if SRAM3 power domain is ON 1 S_PD_SYS_ON Enable PD_SYS ON Sensitivity 0 1 read-write enable Keep PD_SYS awake after powered ON 1 PIDR0 Peripheral ID 0 0xFE0 read-only n 0x54 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 read-only n 0x1B 0xFFFFFFFF PIDR3 Peripheral ID 3 0xFEC read-only n 0x0 0xFFFFFFFF PIDR4 Peripheral ID 4 0xFD0 read-only n 0x4 0xFFFFFFFF RESET_MASK Reset Mask 0x104 read-write n 0x30 0xFFFFFFFF NSWD_EN Enable NON-SECURE WATCHDOG Reset 1 2 read-write disabled Disabled NON-SECURE WATCHDOG Reset 0 enabled Enable NON-SECURE WATCHDOG Reset 1 SYSRSTREQ0_EN Enable Merging CPU 0 System Reset Request 4 5 read-write disabled Disabled Merging CPU 0 System Reset Request 0 enabled Enable Merging CPU 0 System Reset Request 1 SYSRSTREQ1_EN Enable Merging CPU 0 System Reset Request 5 6 read-write disabled Disabled Merging CPU 1 System Reset Request 0 enabled Enable Merging CPU 1 System Reset Request 1 RESET_SYNDROME Reset Syndrome 0x100 read-write n 0x1 0xFFFFFFFF LOCKUP0 CPU 0 Lock-up Status 6 7 write-only LOCKUP1 CPU 1 Lock-up Status 7 8 write-only NSWD Non-secure watchdog 1 2 write-only PoR Power-on 0 1 write-only RESETREQ External Reset Request 8 9 write-only S32KWD Watchdog on the S32KCLK clock 3 4 write-only SWD Secure watchdog 2 3 write-only SWRESETREQ Software Reset Request 9 10 write-only SYSRSTREQ0 CPU 0 System Reset Request 4 5 write-only SYSRSTREQ1 CPU 1 System Reset Request 5 6 write-only SCSECCTRL System Security Control 0xC read-write n 0x0 0xFFFFFFFF CERTDISABLE Control to disable certification path 0 1 enable control to enable certification path 0 disable control to disable certification path 1 CERTDISABLED Indicates that the Certification write path has been disabled 16 17 enabled Certification write path has been enabled 0 disabled Certification write path has been disabled 1 CERTREADEN Control to enable read access on the certification path as long as CERTDISABLE is also LOW 1 2 disable control to disable read access on the certification path as long as CERTDISABLE is also LOW 0 enable control to enable read access on the certification path as long as CERTDISABLE is also LOW 1 CERTREADENABLED Indicates whether the certification read access is enabled 17 18 disabled certification read access is disabled 0 enabled certification read access is enabled 1 SCSECCFGLOCK Control to disable writes to security-related control registers in this register block 2 3 enable control to enable writes to security-related control registers in this register block 0 disable control to disable writes to security-related control registers in this register block 1 SECDBGCLR Secure Debug Configuration Clear 0x8 write-only n 0x0 0xFFFFFFFF DBGEN_I_CLR Debug enable clear control 0 1 disable debug disable clear control 0 enable debug enable clear control 1 DBGEN_SEL_CLR Debug enable selector clear control 1 2 disable debug disable selector clear control 0 enable debug enable selector clear control 1 NIDEN_I_CLR Non-invasive debug enable clear control 2 3 disable non-invasive debug disable clear control 0 enable non-invasive debug enable clear control 1 NIDEN_SEL_CLR Non-invasive debug enable selector clear control 3 4 disable non-invasive debug disable selector clear control 0 enable non-invasive debug enable selector clear control 1 SPIDEN_I_CLR Secure privilege invasive debug enable clear control 4 5 disable Secure privilege invasive debug disable clear control 0 enable Secure privilege invasive debug enable clear control 1 SPIDEN_SEL_CLR Secure privilege invasive debug enable selector clear control 5 6 disable Secure privilege invasive debug disable selector clear control 0 enable Secure privilege invasive debug enable selector clear control 1 SPNIDEN_I_CLR Secure privilege non-invasive debug enable clear control 6 7 disable Secure privilege non-invasive debug disable clear control 0 enable Secure privilege non-invasive debug enable clear control 1 SPNIDEN_SEL_CLR Secure privilege non-invasive debug enable selector clear control 7 8 disable Secure privilege non-invasive debug disable selector clear control 0 enable Secure privilege non-invasive debug enable selector clear control 1 SECDBGSET Secure Debug Configuration Set 0x4 write-only n 0x0 0xFFFFFFFF DBGEN_I_SET High active debug enable set control 0 1 DBGEN_SEL_SET Debug enable selector set control 1 2 disable debug disable selector set control 0 enable debug enable selector set control 1 NIDEN_I_SET Non-invasive debug enable set control 2 3 disable non-invasive debug disable set control 0 enable non-invasive debug enable set control 1 NIDEN_SEL_SET Non-invasive debug enable selector set control 3 4 disable non-invasive debug disable selector set control 0 enable non-invasive debug enable selector set control 1 SPIDEN_I_SET Secure privilege invasive debug enable set control 4 5 disable Secure privilege invasive debug disable set control 0 enable Secure privilege invasive debug enable set control 1 SPIDEN_SEL_SET Secure privilege invasive debug enable selector set control 5 6 disable Secure privilege invasive debug disable selector set control 0 enable Secure privilege invasive debug enable selector set control 1 SPNIDEN_I_SET Secure privilege non-invasive debug enable set control 6 7 disable Secure privilege non-invasive debug disable set control 0 enable Secure privilege non-invasive debug enable set control 1 SPNIDEN_SEL_SET Secure privilege non-invasive debug enable selector set control 7 8 disable Secure privilege non-invasive debug disable selector set control 0 enable Secure privilege non-invasive debug enable selector set control 1 SECDBGSTAT Secure Debug Configuration Status 0x0 read-only n 0x0 0xFFFFFFFF DBGEN_I_STATUS Debug enable value 0 1 disable debug disable 0 enable debug enable 1 DBGEN_SEL_STATUS Debug enable selector value 1 2 disable debug disable selector 0 enable debug enable selector 1 NIDEN_I_STATUS Non-invasive debug enable value 2 3 disable non-invasive debug disable 0 enable non-invasive debug enable 1 NIDEN_SEL_STATUS Non-invasive debug enable selector value 3 4 disable non-invasive debug disable selector 0 enable non-invasive debug enable selector 1 SPIDEN_I_STATUS Secure privilege invasive debug enable value 4 5 disable Secure privilege invasive debug disable 0 enable Secure privilege invasive debug enable 1 SPIDEN_SEL_STATUS Secure privilege invasive debug enable selector value 5 6 disable Secure privilege invasive debug disable selector 0 enable Secure privilege invasive debug enable selector 1 SPNIDEN_SEL_STATUS Secure privilege non-invasive debug enable selector value 7 8 disable Secure privilege non-invasive debug disable selector 0 enable Secure privilege non-invasive debug enable selector 1 SPNIDEN_STATUS Secure privilege non-invasive debug enable value 6 7 disable Secure privilege non-invasive debug disable 0 enable Secure privilege non-invasive debug enable 1 SWRESET Software Reset 0x108 write-only n 0x0 0xFFFFFFFF SWRESETREQ High Active Software Reset Request 9 10 write-only SYSCLK_DIV System Clock Divider Configuration 0x14 read-write n 0x0 0xFFFFFFFF SYSCLKDIV SYSCLK from FCLK Clock Divider Ratio Request 0 5 SYSCLKDIV_CUR Clock Divider Current Value 16 21 read-only WICCTRL WIC request and acknowledge handshake 0x120 read-write n 0x0 0xFFFFFFFF CPU0WICEN_CLR High Active CPU 0 WIC Enable Request Clear 8 9 write-only CPU0WICEN_SET High Active CPU 0 WIC Enable Request Set 4 5 write-only CPU0WICEN_STATUS CPU 0 WIC Enable Request Status 0 1 read-only disabled CPU 0 WIC request disabled 0 enable CPU 0 WIC request enabled 1 CPU0WICRDY CPU 0 WIC Enable Acknowledge 16 17 read-only disabled CPU 0 WIC Disabled 0 enabled CPU 0 WIC Enabled 1 CPU1WICEN_CLR High Active CPU 1 WIC Enable Request Clear 9 10 write-only CPU1WICEN_SET High Active CPU 1 WIC Enable Request Set 5 6 write-only CPU1WICEN_STATUS CPU 1 WIC Enable Request Status 1 2 read-only disabled CPU 1 WIC request disabled 0 enable CPU 1 WIC request enabled 1 CPU1WICRDY CPU 1 WIC Enable Acknowledge 17 18 read-only disabled CPU 1 WIC Disabled 0 enabled CPU 1 WIC Enabled 1 TIMER0 Timer 0 Timer 0x40000000 0x0 0x10 registers n TIMER0 Timer 0 3 CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ENABLE Enable 0 1 Disable Timer is disabled 0 Enable Timer is enabled 1 EXTCLK External Clock Enable 2 3 Disable External Clock is disabled 0 Enable External Clock is enabled 1 EXTIN External Input as Enable 1 2 Disable External Input as Enable is disabled 0 Enable External Input as Enable is enabled 1 INTEN Interrupt Enable 3 4 Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 INTCLEAR Timer Interrupt clear register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF oneToClear INTSTATUS Timer Interrupt status register 0xC read-only n 0x0 0xFFFFFFFF RELOAD Counter Reload Value 0x8 read-write n 0x0 0xFFFFFFFF VALUE Current Timer Counter Value 0x4 read-write n 0x0 0xFFFFFFFF TIMER0_Secure Timer 0 (Secure) Timer 0x50000000 0x0 0x10 registers n CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ENABLE Enable 0 1 Disable Timer is disabled 0 Enable Timer is enabled 1 EXTCLK External Clock Enable 2 3 Disable External Clock is disabled 0 Enable External Clock is enabled 1 EXTIN External Input as Enable 1 2 Disable External Input as Enable is disabled 0 Enable External Input as Enable is enabled 1 INTEN Interrupt Enable 3 4 Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 INTCLEAR Timer Interrupt clear register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF oneToClear INTSTATUS Timer Interrupt status register 0xC read-only n 0x0 0xFFFFFFFF RELOAD Counter Reload Value 0x8 read-write n 0x0 0xFFFFFFFF VALUE Current Timer Counter Value 0x4 read-write n 0x0 0xFFFFFFFF TIMER1 Timer 1 Timer 0x40001000 0x0 0x10 registers n TIMER1 Timer 1 4 CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ENABLE Enable 0 1 Disable Timer is disabled 0 Enable Timer is enabled 1 EXTCLK External Clock Enable 2 3 Disable External Clock is disabled 0 Enable External Clock is enabled 1 EXTIN External Input as Enable 1 2 Disable External Input as Enable is disabled 0 Enable External Input as Enable is enabled 1 INTEN Interrupt Enable 3 4 Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 INTCLEAR Timer Interrupt clear register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF oneToClear INTSTATUS Timer Interrupt status register 0xC read-only n 0x0 0xFFFFFFFF RELOAD Counter Reload Value 0x8 read-write n 0x0 0xFFFFFFFF VALUE Current Timer Counter Value 0x4 read-write n 0x0 0xFFFFFFFF TIMER1_Secure Timer 1 (Secure) LSICNT 0x50001000 0x0 0x64 registers n BRMPCON - 0x8 32 read-write n 0x0 0x0 PDEN - 0 1 read-write CLKCON - 0x4C 32 read-write n 0x0 0x0 CAES - 22 23 read-write CCMP0 - 30 31 read-write CCMP1 - 31 32 read-write CDMAC - 29 30 read-write CFTM0 - 8 9 read-write CFTM1 - 9 10 read-write CFTM2 - 10 11 read-write CFTM3 - 11 12 read-write CI2C1 - 20 21 read-write CI2CF0 - 21 22 read-write CLCD - 25 26 read-write CRAD - 14 15 read-write CRND - 23 24 read-write CRTC - 26 27 read-write CSAD - 13 14 read-write CSIO0 - 16 17 read-write CSIOF0 - 17 18 read-write CTM0 - 0 1 read-write CTM1 - 1 2 read-write CTM1K - 15 16 read-write CTM2 - 2 3 read-write CTM3 - 3 4 read-write CTM4 - 4 5 read-write CTM5 - 5 6 read-write CTM6 - 6 7 read-write CTM7 - 7 8 read-write CUA0 - 18 19 read-write CUAF0 - 19 20 read-write CUSB - 24 25 read-write CVLS - 27 28 read-write DREQSEL - 0x4 32 read-write n 0x0 0x0 DREQ0SEL - 0 4 read-write DREQ1SEL - 8 12 read-write IDR - 0x0 32 read-write n 0x0 0x0 PID - 4 32 read-only PRV - 0 4 read-only PMCON - 0x48 32 read-write n 0x0 0x0 LXTHVN - 2 3 read-write UDHEN - 0 1 read-write UDHON - 1 2 read-write REMAPBASE - 0x14 32 read-write n 0x0 0x0 REMAP_BASE - 12 30 read-write REMAPCON - 0x10 32 read-write n 0x0 0x0 REMAP - 0 4 read-write REMAP_EN - 4 5 read-write RSTCON - 0x50 32 read-write n 0x0 0x0 RAES - 22 23 read-write RCMP0 - 30 31 read-write RCMP1 - 31 32 read-write RDMAC - 29 30 read-write RFTM0 - 8 9 read-write RFTM1 - 9 10 read-write RFTM2 - 10 11 read-write RFTM3 - 11 12 read-write RI2C1 - 20 21 read-write RI2CF0 - 21 22 read-write RLCD - 25 26 read-write RLLD - 28 29 read-write RRAD - 14 15 read-write RRND - 23 24 read-write RRTC - 26 27 read-write RSAD - 13 14 read-write RSIO0 - 16 17 read-write RSIOF0 - 17 18 read-write RTM0 - 0 1 read-write RTM1 - 1 2 read-write RTM1K - 15 16 read-write RTM2 - 2 3 read-write RTM3 - 3 4 read-write RTM4 - 4 5 read-write RTM5 - 5 6 read-write RTM6 - 6 7 read-write RTM7 - 7 8 read-write RUA0 - 18 19 read-write RUAF0 - 19 20 read-write RUSB - 24 25 read-write RVLS - 27 28 read-write SBYCON - 0x44 32 read-write n 0x0 0x0 DHLT - 2 3 read-write HLT - 0 1 read-write HLTH - 3 4 read-write TESTREG - 0x30 32 read-write n 0x0 0x0 MOP - 0 4 read-write UART0 UART 0 UART 0x40105000 0x0 0x4C registers n UARTINTR0 UART0 interrupt 44 UARTCR Control register 0x30 read-write n 0x300 0xFFFFFFFF CTSEn CTS hardware flow control enable 15 1 Disable CTS hardware flow control is disabled 0 Enable CTS hardware flow control is enabled 1 DTR Data transmit ready 10 1 LBE Loop back enable 7 1 Disable Loop back mode is disabled 0 Enable Loop back mode is enabled 1 Out1 Complement of the UART Out1 12 1 Out2 Complement of the UART Out2 13 1 RTS Request to send 11 1 RTSEn RTS hardware flow control enable 14 1 Disable RTS hardware flow control is disabled 0 Enable RTS hardware flow control is enabled 1 RXE Receive enable 9 1 Disable Reception is disabled 0 Enable Reception is enabled 1 SIREN SIR enable 1 1 Disable SIR is disabled 0 Enable SIR is enabled 1 SIRLP IrDA SIR low power mode 2 1 Disable SIR low power mode is disabled 0 Enable SIR low power mode is enabled 1 TXE Transmit enable 8 1 Disable Transmission is disabled. 0 Enable Transmission is enabled. 1 UARTEN UART enable 0 1 Disable UART is disabled 0 Enable UART is enabled 1 UARTDMACR DMA control register 0x48 read-write n 0x0 0xFFFFFFFF DMAONERR DMA on error 2 1 Disable DMA receive request outputs are enabled when the UART error interrupt is asserted 0 Enable DMA receive request outputs are disabled when the UART error interrupt is asserted 1 RXDMAE Receive DMA enable 0 1 Disable Receive DMA is disabled 0 Enable Receive DMA is enabled 1 TXDMAE Transmit DMA enable 1 1 Disable Transmit DMA is disabled 0 Enable Transmit DMA is enabled 1 UARTDR Data register 0x0 read-write n 0x0 0xFFFFFFFF BE Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time 10 1 Data Receive/Transmit data 0 8 FE Framing error: Indicates the received character did not had a valid stop bit 8 1 OE Overrun error: Indicates if data is received and the receive FIFO is already full. 11 1 PE Parity error: Indicates that the parity of the received data character does not match the parity selected 9 1 UARTFBRD Fractional baud rate register 0x28 read-write n 0x0 0xFFFFFFFF BAUD_DIVINT The integer baud rate divisor 0 6 UARTIBRD Integer baud rate register 0x24 read-write n 0x0 0xFFFFFFFF BAUD_DIVINT The integer baud rate divisor 0 16 UARTICR Interrupt clear register 0x44 write-only n 0x0 0xFFFFFFFF BEIC Break error interrupt clear, write 1 to clear, write 0 has no effect 9 1 CTSMIC nUARTCTS modem interrupt clear, write 1 to clear, write 0 has no effect 1 1 DCDMIC nUARTDCD modem interrupt clear, write 1 to clear, write 0 has no effect 2 1 DSRIC nUARTDSR modem interrupt clear, write 1 to clear, write 0 has no effect 3 1 FEIC Framing error interrupt clear, write 1 to clear, write 0 has no effect 7 1 OEIC Overrun error interrupt clear, write 1 to clear, write 0 has no effect 10 1 PEIC Parity error interrupt clear, write 1 to clear, write 0 has no effect 8 1 RIMIC nUARTRI modem interrupt clear, write 1 to clear, write 0 has no effect 0 1 RTIC Receive timeout interrupt clear, write 1 to clear, write 0 has no effect 6 1 RXIC Receive interrupt clear, write 1 to clear, write 0 has no effect 4 1 TXIC Transmit interrupt clear, write 1 to clear, write 0 has no effect 5 1 UARTIFLS Interrupt FIFO level select register 0x34 read-write n 0x12 0xFFFFFFFF RXIFLSEL Receive interrupt FIFO level select 3 3 1/8 full Receive FIFO becomes greater than or equal to 1/8 full 0 1/4 full Receive FIFO becomes greater than or equal to 1/4 full 1 1/2 full Receive FIFO becomes greater than or equal to 1/2 full 2 3/4 full Receive FIFO becomes greater than or equal to 3/4 full 3 7/8 full Receive FIFO becomes greater than or equal to 7/8 full 4 TXIFLSEL Transmit interrupt FIFO level select 0 3 1/8 full Transmit FIFO becomes less than or equal to 1/8 full 0 1/4 full Transmit FIFO becomes less than or equal to 1/4 full 1 1/2 full Transmit FIFO becomes less than or equal to 1/2 full 2 3/4 full Transmit FIFO becomes less than or equal to 3/4 full 3 7/8 full Transmit FIFO becomes less than or equal to 7/8 full 4 UARTILPR IrDA low-power counter register 0x20 read-write n 0x0 0xFFFFFFFF ILPDVSR 8-bit low-power divisor value 0 8 UARTIMSC Interrupt mask set/clear register 0x38 read-write n 0x0 0xFFFFFFFF BEIM Break error interrupt mask 9 1 Clear Clears the mask 0 Set Sets the mask 1 CTSMIM nUARTCTS modem interrupt mask. 1 1 Clear Clears the mask 0 Set Sets the mask 1 DCDMIM nUARTDCD modem interrupt mask 2 1 Clear Clears the mask 0 Set Sets the mask 1 DSRMIM nUARTDSR modem interrupt mask 3 1 Clear Clears the mask 0 Set Sets the mask 1 FEIM Framing error interrupt mask 7 1 Clear Clears the mask 0 Set Sets the mask 1 OEIM Overrun error interrupt mask 10 1 Clear Clears the mask 0 Set Sets the mask 1 PEIM Parity error interrupt mask 8 1 Clear Clears the mask 0 Set Sets the mask 1 RIMIM nUARTRI modem interrupt mask 0 1 Clear Clears the mask 0 Set Sets the mask 1 RTIM Receive timeout interrupt mask 6 1 Clear Clears the mask 0 Set Sets the mask 1 RXIM Receive interrupt mask 4 1 Clear Clears the mask 0 Set Sets the mask 1 TXIM Transmit interrupt mask 5 1 Clear Clears the mask 0 Set Sets the mask 1 UARTLCR_H Line control register 0x2C read-write n 0x0 0xFFFFFFFF BRK Send break 0 1 EPS Even parity select 2 1 FEN Enable FIFOs 4 1 PEN Parity enable 1 1 SPS Stick parity select 7 1 STP2 Two stop bits select 3 1 WLEN Word length 5 2 UARTMIS Masked interrupt status register 0x40 read-only n 0x0 0xFFFFFFFF BEMIS Break error masked interrupt status 9 1 CTSMMIS nUARTCTS modem masked interrupt status. 1 1 DCDMMIS nUARTDCD modem masked interrupt status 2 1 DSRMMIS nUARTDSR modem masked interrupt status 3 1 FEMIS Framing error masked interrupt status 7 1 OEMIS Overrun error masked interrupt status 10 1 PEMIS Parity error masked interrupt status 8 1 RIMMIS nUARTRI modem masked interrupt status 0 1 RTMIS Receive timeout masked interrupt status 6 1 RXMIS Receive masked interrupt status 4 1 TXMIS Transmit masked interrupt status 5 1 UARTRFR Flag register 0x18 read-only n 0x0 0xFFFFFFFF BUSY UART busy 3 1 CTS Clear to send 0 1 DCD Data carrier detect 2 1 DSR Data set ready 1 1 RI Ring indicator 8 1 RXFE Receive FIFO empty 4 1 RXFF Receive FIFO full 6 1 TXFE Transmit FIFO empty 7 1 TXFF Transmit FIFO full 5 1 UARTRIS Raw interrupt status register 0x3C read-only n 0x0 0xFFFFFFFF BERIS Break error interrupt status 9 1 CTSRMIS nUARTCTS modem interrupt status. 1 1 DCDRMIS nUARTDCD modem interrupt status 2 1 DSRRMIS nUARTDSR modem interrupt status 3 1 FERIS Framing error interrupt status 7 1 OERIS Overrun error interrupt status 10 1 PERIS Parity error interrupt status 8 1 RIRMIS nUARTRI modem interrupt status 0 1 RTRIS Receive timeout interrupt status 6 1 RXRIS Receive interrupt status 4 1 TXRIS Transmit interrupt status 5 1 UARTRSR_UARTECR Receive status register/error clear register 0x4 read-write n 0x0 0xFFFFFFFF BE Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time 2 1 FE Framing error: Indicates the received character did not had a valid stop bit 0 1 OE Overrunerror: Indicates if data is received and the receive FIFO is already full. 3 1 PE Parity error: Indicates that the parity of the received data character does not match the parity selected 1 1 UART0_Secure UART 0 (Secure) UART 0x50105000 0x0 0x4C registers n UARTCR Control register 0x30 read-write n 0x300 0xFFFFFFFF CTSEn CTS hardware flow control enable 15 1 Disable CTS hardware flow control is disabled 0 Enable CTS hardware flow control is enabled 1 DTR Data transmit ready 10 1 LBE Loop back enable 7 1 Disable Loop back mode is disabled 0 Enable Loop back mode is enabled 1 Out1 Complement of the UART Out1 12 1 Out2 Complement of the UART Out2 13 1 RTS Request to send 11 1 RTSEn RTS hardware flow control enable 14 1 Disable RTS hardware flow control is disabled 0 Enable RTS hardware flow control is enabled 1 RXE Receive enable 9 1 Disable Reception is disabled 0 Enable Reception is enabled 1 SIREN SIR enable 1 1 Disable SIR is disabled 0 Enable SIR is enabled 1 SIRLP IrDA SIR low power mode 2 1 Disable SIR low power mode is disabled 0 Enable SIR low power mode is enabled 1 TXE Transmit enable 8 1 Disable Transmission is disabled. 0 Enable Transmission is enabled. 1 UARTEN UART enable 0 1 Disable UART is disabled 0 Enable UART is enabled 1 UARTDMACR DMA control register 0x48 read-write n 0x0 0xFFFFFFFF DMAONERR DMA on error 2 1 Disable DMA receive request outputs are enabled when the UART error interrupt is asserted 0 Enable DMA receive request outputs are disabled when the UART error interrupt is asserted 1 RXDMAE Receive DMA enable 0 1 Disable Receive DMA is disabled 0 Enable Receive DMA is enabled 1 TXDMAE Transmit DMA enable 1 1 Disable Transmit DMA is disabled 0 Enable Transmit DMA is enabled 1 UARTDR Data register 0x0 read-write n 0x0 0xFFFFFFFF BE Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time 10 1 Data Receive/Transmit data 0 8 FE Framing error: Indicates the received character did not had a valid stop bit 8 1 OE Overrun error: Indicates if data is received and the receive FIFO is already full. 11 1 PE Parity error: Indicates that the parity of the received data character does not match the parity selected 9 1 UARTFBRD Fractional baud rate register 0x28 read-write n 0x0 0xFFFFFFFF BAUD_DIVINT The integer baud rate divisor 0 6 UARTIBRD Integer baud rate register 0x24 read-write n 0x0 0xFFFFFFFF BAUD_DIVINT The integer baud rate divisor 0 16 UARTICR Interrupt clear register 0x44 write-only n 0x0 0xFFFFFFFF BEIC Break error interrupt clear, write 1 to clear, write 0 has no effect 9 1 CTSMIC nUARTCTS modem interrupt clear, write 1 to clear, write 0 has no effect 1 1 DCDMIC nUARTDCD modem interrupt clear, write 1 to clear, write 0 has no effect 2 1 DSRIC nUARTDSR modem interrupt clear, write 1 to clear, write 0 has no effect 3 1 FEIC Framing error interrupt clear, write 1 to clear, write 0 has no effect 7 1 OEIC Overrun error interrupt clear, write 1 to clear, write 0 has no effect 10 1 PEIC Parity error interrupt clear, write 1 to clear, write 0 has no effect 8 1 RIMIC nUARTRI modem interrupt clear, write 1 to clear, write 0 has no effect 0 1 RTIC Receive timeout interrupt clear, write 1 to clear, write 0 has no effect 6 1 RXIC Receive interrupt clear, write 1 to clear, write 0 has no effect 4 1 TXIC Transmit interrupt clear, write 1 to clear, write 0 has no effect 5 1 UARTIFLS Interrupt FIFO level select register 0x34 read-write n 0x12 0xFFFFFFFF RXIFLSEL Receive interrupt FIFO level select 3 3 1/8 full Receive FIFO becomes greater than or equal to 1/8 full 0 1/4 full Receive FIFO becomes greater than or equal to 1/4 full 1 1/2 full Receive FIFO becomes greater than or equal to 1/2 full 2 3/4 full Receive FIFO becomes greater than or equal to 3/4 full 3 7/8 full Receive FIFO becomes greater than or equal to 7/8 full 4 TXIFLSEL Transmit interrupt FIFO level select 0 3 1/8 full Transmit FIFO becomes less than or equal to 1/8 full 0 1/4 full Transmit FIFO becomes less than or equal to 1/4 full 1 1/2 full Transmit FIFO becomes less than or equal to 1/2 full 2 3/4 full Transmit FIFO becomes less than or equal to 3/4 full 3 7/8 full Transmit FIFO becomes less than or equal to 7/8 full 4 UARTILPR IrDA low-power counter register 0x20 read-write n 0x0 0xFFFFFFFF ILPDVSR 8-bit low-power divisor value 0 8 UARTIMSC Interrupt mask set/clear register 0x38 read-write n 0x0 0xFFFFFFFF BEIM Break error interrupt mask 9 1 Clear Clears the mask 0 Set Sets the mask 1 CTSMIM nUARTCTS modem interrupt mask. 1 1 Clear Clears the mask 0 Set Sets the mask 1 DCDMIM nUARTDCD modem interrupt mask 2 1 Clear Clears the mask 0 Set Sets the mask 1 DSRMIM nUARTDSR modem interrupt mask 3 1 Clear Clears the mask 0 Set Sets the mask 1 FEIM Framing error interrupt mask 7 1 Clear Clears the mask 0 Set Sets the mask 1 OEIM Overrun error interrupt mask 10 1 Clear Clears the mask 0 Set Sets the mask 1 PEIM Parity error interrupt mask 8 1 Clear Clears the mask 0 Set Sets the mask 1 RIMIM nUARTRI modem interrupt mask 0 1 Clear Clears the mask 0 Set Sets the mask 1 RTIM Receive timeout interrupt mask 6 1 Clear Clears the mask 0 Set Sets the mask 1 RXIM Receive interrupt mask 4 1 Clear Clears the mask 0 Set Sets the mask 1 TXIM Transmit interrupt mask 5 1 Clear Clears the mask 0 Set Sets the mask 1 UARTLCR_H Line control register 0x2C read-write n 0x0 0xFFFFFFFF BRK Send break 0 1 EPS Even parity select 2 1 FEN Enable FIFOs 4 1 PEN Parity enable 1 1 SPS Stick parity select 7 1 STP2 Two stop bits select 3 1 WLEN Word length 5 2 UARTMIS Masked interrupt status register 0x40 read-only n 0x0 0xFFFFFFFF BEMIS Break error masked interrupt status 9 1 CTSMMIS nUARTCTS modem masked interrupt status. 1 1 DCDMMIS nUARTDCD modem masked interrupt status 2 1 DSRMMIS nUARTDSR modem masked interrupt status 3 1 FEMIS Framing error masked interrupt status 7 1 OEMIS Overrun error masked interrupt status 10 1 PEMIS Parity error masked interrupt status 8 1 RIMMIS nUARTRI modem masked interrupt status 0 1 RTMIS Receive timeout masked interrupt status 6 1 RXMIS Receive masked interrupt status 4 1 TXMIS Transmit masked interrupt status 5 1 UARTRFR Flag register 0x18 read-only n 0x0 0xFFFFFFFF BUSY UART busy 3 1 CTS Clear to send 0 1 DCD Data carrier detect 2 1 DSR Data set ready 1 1 RI Ring indicator 8 1 RXFE Receive FIFO empty 4 1 RXFF Receive FIFO full 6 1 TXFE Transmit FIFO empty 7 1 TXFF Transmit FIFO full 5 1 UARTRIS Raw interrupt status register 0x3C read-only n 0x0 0xFFFFFFFF BERIS Break error interrupt status 9 1 CTSRMIS nUARTCTS modem interrupt status. 1 1 DCDRMIS nUARTDCD modem interrupt status 2 1 DSRRMIS nUARTDSR modem interrupt status 3 1 FERIS Framing error interrupt status 7 1 OERIS Overrun error interrupt status 10 1 PERIS Parity error interrupt status 8 1 RIRMIS nUARTRI modem interrupt status 0 1 RTRIS Receive timeout interrupt status 6 1 RXRIS Receive interrupt status 4 1 TXRIS Transmit interrupt status 5 1 UARTRSR_UARTECR Receive status register/error clear register 0x4 read-write n 0x0 0xFFFFFFFF BE Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time 2 1 FE Framing error: Indicates the received character did not had a valid stop bit 0 1 OE Overrunerror: Indicates if data is received and the receive FIFO is already full. 3 1 PE Parity error: Indicates that the parity of the received data character does not match the parity selected 1 1 UART1 UART 1 UART 0x40106000 0x0 0x4C registers n UARTINTR1 UART1 interrupt 50 UARTCR Control register 0x30 read-write n 0x300 0xFFFFFFFF CTSEn CTS hardware flow control enable 15 1 Disable CTS hardware flow control is disabled 0 Enable CTS hardware flow control is enabled 1 DTR Data transmit ready 10 1 LBE Loop back enable 7 1 Disable Loop back mode is disabled 0 Enable Loop back mode is enabled 1 Out1 Complement of the UART Out1 12 1 Out2 Complement of the UART Out2 13 1 RTS Request to send 11 1 RTSEn RTS hardware flow control enable 14 1 Disable RTS hardware flow control is disabled 0 Enable RTS hardware flow control is enabled 1 RXE Receive enable 9 1 Disable Reception is disabled 0 Enable Reception is enabled 1 SIREN SIR enable 1 1 Disable SIR is disabled 0 Enable SIR is enabled 1 SIRLP IrDA SIR low power mode 2 1 Disable SIR low power mode is disabled 0 Enable SIR low power mode is enabled 1 TXE Transmit enable 8 1 Disable Transmission is disabled. 0 Enable Transmission is enabled. 1 UARTEN UART enable 0 1 Disable UART is disabled 0 Enable UART is enabled 1 UARTDMACR DMA control register 0x48 read-write n 0x0 0xFFFFFFFF DMAONERR DMA on error 2 1 Disable DMA receive request outputs are enabled when the UART error interrupt is asserted 0 Enable DMA receive request outputs are disabled when the UART error interrupt is asserted 1 RXDMAE Receive DMA enable 0 1 Disable Receive DMA is disabled 0 Enable Receive DMA is enabled 1 TXDMAE Transmit DMA enable 1 1 Disable Transmit DMA is disabled 0 Enable Transmit DMA is enabled 1 UARTDR Data register 0x0 read-write n 0x0 0xFFFFFFFF BE Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time 10 1 Data Receive/Transmit data 0 8 FE Framing error: Indicates the received character did not had a valid stop bit 8 1 OE Overrun error: Indicates if data is received and the receive FIFO is already full. 11 1 PE Parity error: Indicates that the parity of the received data character does not match the parity selected 9 1 UARTFBRD Fractional baud rate register 0x28 read-write n 0x0 0xFFFFFFFF BAUD_DIVINT The integer baud rate divisor 0 6 UARTIBRD Integer baud rate register 0x24 read-write n 0x0 0xFFFFFFFF BAUD_DIVINT The integer baud rate divisor 0 16 UARTICR Interrupt clear register 0x44 write-only n 0x0 0xFFFFFFFF BEIC Break error interrupt clear, write 1 to clear, write 0 has no effect 9 1 CTSMIC nUARTCTS modem interrupt clear, write 1 to clear, write 0 has no effect 1 1 DCDMIC nUARTDCD modem interrupt clear, write 1 to clear, write 0 has no effect 2 1 DSRIC nUARTDSR modem interrupt clear, write 1 to clear, write 0 has no effect 3 1 FEIC Framing error interrupt clear, write 1 to clear, write 0 has no effect 7 1 OEIC Overrun error interrupt clear, write 1 to clear, write 0 has no effect 10 1 PEIC Parity error interrupt clear, write 1 to clear, write 0 has no effect 8 1 RIMIC nUARTRI modem interrupt clear, write 1 to clear, write 0 has no effect 0 1 RTIC Receive timeout interrupt clear, write 1 to clear, write 0 has no effect 6 1 RXIC Receive interrupt clear, write 1 to clear, write 0 has no effect 4 1 TXIC Transmit interrupt clear, write 1 to clear, write 0 has no effect 5 1 UARTIFLS Interrupt FIFO level select register 0x34 read-write n 0x12 0xFFFFFFFF RXIFLSEL Receive interrupt FIFO level select 3 3 1/8 full Receive FIFO becomes greater than or equal to 1/8 full 0 1/4 full Receive FIFO becomes greater than or equal to 1/4 full 1 1/2 full Receive FIFO becomes greater than or equal to 1/2 full 2 3/4 full Receive FIFO becomes greater than or equal to 3/4 full 3 7/8 full Receive FIFO becomes greater than or equal to 7/8 full 4 TXIFLSEL Transmit interrupt FIFO level select 0 3 1/8 full Transmit FIFO becomes less than or equal to 1/8 full 0 1/4 full Transmit FIFO becomes less than or equal to 1/4 full 1 1/2 full Transmit FIFO becomes less than or equal to 1/2 full 2 3/4 full Transmit FIFO becomes less than or equal to 3/4 full 3 7/8 full Transmit FIFO becomes less than or equal to 7/8 full 4 UARTILPR IrDA low-power counter register 0x20 read-write n 0x0 0xFFFFFFFF ILPDVSR 8-bit low-power divisor value 0 8 UARTIMSC Interrupt mask set/clear register 0x38 read-write n 0x0 0xFFFFFFFF BEIM Break error interrupt mask 9 1 Clear Clears the mask 0 Set Sets the mask 1 CTSMIM nUARTCTS modem interrupt mask. 1 1 Clear Clears the mask 0 Set Sets the mask 1 DCDMIM nUARTDCD modem interrupt mask 2 1 Clear Clears the mask 0 Set Sets the mask 1 DSRMIM nUARTDSR modem interrupt mask 3 1 Clear Clears the mask 0 Set Sets the mask 1 FEIM Framing error interrupt mask 7 1 Clear Clears the mask 0 Set Sets the mask 1 OEIM Overrun error interrupt mask 10 1 Clear Clears the mask 0 Set Sets the mask 1 PEIM Parity error interrupt mask 8 1 Clear Clears the mask 0 Set Sets the mask 1 RIMIM nUARTRI modem interrupt mask 0 1 Clear Clears the mask 0 Set Sets the mask 1 RTIM Receive timeout interrupt mask 6 1 Clear Clears the mask 0 Set Sets the mask 1 RXIM Receive interrupt mask 4 1 Clear Clears the mask 0 Set Sets the mask 1 TXIM Transmit interrupt mask 5 1 Clear Clears the mask 0 Set Sets the mask 1 UARTLCR_H Line control register 0x2C read-write n 0x0 0xFFFFFFFF BRK Send break 0 1 EPS Even parity select 2 1 FEN Enable FIFOs 4 1 PEN Parity enable 1 1 SPS Stick parity select 7 1 STP2 Two stop bits select 3 1 WLEN Word length 5 2 UARTMIS Masked interrupt status register 0x40 read-only n 0x0 0xFFFFFFFF BEMIS Break error masked interrupt status 9 1 CTSMMIS nUARTCTS modem masked interrupt status. 1 1 DCDMMIS nUARTDCD modem masked interrupt status 2 1 DSRMMIS nUARTDSR modem masked interrupt status 3 1 FEMIS Framing error masked interrupt status 7 1 OEMIS Overrun error masked interrupt status 10 1 PEMIS Parity error masked interrupt status 8 1 RIMMIS nUARTRI modem masked interrupt status 0 1 RTMIS Receive timeout masked interrupt status 6 1 RXMIS Receive masked interrupt status 4 1 TXMIS Transmit masked interrupt status 5 1 UARTRFR Flag register 0x18 read-only n 0x0 0xFFFFFFFF BUSY UART busy 3 1 CTS Clear to send 0 1 DCD Data carrier detect 2 1 DSR Data set ready 1 1 RI Ring indicator 8 1 RXFE Receive FIFO empty 4 1 RXFF Receive FIFO full 6 1 TXFE Transmit FIFO empty 7 1 TXFF Transmit FIFO full 5 1 UARTRIS Raw interrupt status register 0x3C read-only n 0x0 0xFFFFFFFF BERIS Break error interrupt status 9 1 CTSRMIS nUARTCTS modem interrupt status. 1 1 DCDRMIS nUARTDCD modem interrupt status 2 1 DSRRMIS nUARTDSR modem interrupt status 3 1 FERIS Framing error interrupt status 7 1 OERIS Overrun error interrupt status 10 1 PERIS Parity error interrupt status 8 1 RIRMIS nUARTRI modem interrupt status 0 1 RTRIS Receive timeout interrupt status 6 1 RXRIS Receive interrupt status 4 1 TXRIS Transmit interrupt status 5 1 UARTRSR_UARTECR Receive status register/error clear register 0x4 read-write n 0x0 0xFFFFFFFF BE Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time 2 1 FE Framing error: Indicates the received character did not had a valid stop bit 0 1 OE Overrunerror: Indicates if data is received and the receive FIFO is already full. 3 1 PE Parity error: Indicates that the parity of the received data character does not match the parity selected 1 1 UART1_Secure UART 1 (Secure) DMAC 0x50106000 0x0 0xC registers n DMAINT DMA end status register 0x8 32 read-write n 0x0 0x0 IREQ - 0 2 read-only ISTA - 8 10 read-only ISTP - 16 18 read-only DMAMOD DMA mode register 0x0 32 read-write n 0x0 0x0 PRI - 0 1 read-write DMASTA DMA status register 0x4 32 read-write n 0x0 0x0 STA - 0 2 read-only WATCHDOG Non-secure Watchdog Timer WATCHDOG 0x40081000 0x0 0xC04 registers n NONSEC_WATCHDOG_IRQ Non-Secure Watchdog Interrupt 1 WDOGCONTROL Watchdog Control Register 0x8 read-write n 0x0 0xFFFFFFFF INTEN Enable the interrupt event 0 1 Disable Disable Watchdog interrupt 0 Enable Enable Watchdog interrupt. 1 RESEN Enable watchdog reset output 1 1 Disable Disable Watchdog reset 0 Enable Enable Watchdog reset 1 WDOGINTCLR Watchdog Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear WDOGLOAD Watchdog Load Register 0x0 read-write n 0xFFFFFFFF 0xFFFFFFFF WDOGLOCK Watchdog Lock Register 0xC00 read-write n 0x0 0xFFFFFFFF Access Enable register writes 1 31 Status Register write enable status 0 1 Enabled Write access to all other registers is enabled. This is the default. 0 Disabled Write access to all other registers is disabled. 1 WDOGMIS Watchdog Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Watchdog Interrupt 0 1 WDOGRIS Watchdog Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw watchdog Interrupt 0 1 WDOGVALUE Watchdog Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF WATCHDOG_Secure Watchdog (Secure) WATCHDOG 0x50081000 0x0 0xC04 registers n WDOGCONTROL Watchdog Control Register 0x8 read-write n 0x0 0xFFFFFFFF INTEN Enable the interrupt event 0 1 Disable Disable Watchdog interrupt 0 Enable Enable Watchdog interrupt. 1 RESEN Enable watchdog reset output 1 1 Disable Disable Watchdog reset 0 Enable Enable Watchdog reset 1 WDOGINTCLR Watchdog Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear WDOGLOAD Watchdog Load Register 0x0 read-write n 0xFFFFFFFF 0xFFFFFFFF WDOGLOCK Watchdog Lock Register 0xC00 read-write n 0x0 0xFFFFFFFF Access Enable register writes 1 31 Status Register write enable status 0 1 Enabled Write access to all other registers is enabled. This is the default. 0 Disabled Write access to all other registers is disabled. 1 WDOGMIS Watchdog Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Watchdog Interrupt 0 1 WDOGRIS Watchdog Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw watchdog Interrupt 0 1 WDOGVALUE Watchdog Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF